PCF8531U NXP [NXP Semiconductors], PCF8531U Datasheet - Page 32

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PCF8531U

Manufacturer Part Number
PCF8531U
Description
34 x 128 pixel matrix driver
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
14. Dynamic characteristics
Table 16.
V
to +85 C; unless otherwise specified.
[1]
[2]
[3]
[4]
PCF8531_4
Product data sheet
Symbol
f
f
f
t
t
Serial bus interface (see
f
t
t
t
t
t
t
C
t
t
t
t
t
fr(LCD)
osc
clk(ext)
w(RESL)
su(RESL)
SCL
LOW
HIGH
SU;DAT
HD;DAT
r
f
SU;STA
HD;STA
SU;STO
SP
BUF
DD1
Fig 20. Reset timing
b
f
A reset is generated if t
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V
input voltage swing of V
C
fr
= 1.8 V (1.9 V) to 5.5 V; V
b
= f
= total capacitance of one bus line in pF.
clk(ext)
Dynamic characteristics
Parameter
LCD frame frequency
oscillator frequency
external clock frequency
RES LOW pulse width
RES LOW set-up time
SCL clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
data set-up time
data hold time
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
set-up time for a repeated START condition
hold time (repeated) START condition
set-up time for STOP condition
pulse width of spikes that must be
suppressed by the input filter
bus free time between a STOP and START
condition
/480 or f
osc
RES
V
/480.
DD
w(RESL)
SS
Figure
to V
DD2
DD
3 ns (see
.
21)
and V
[3]
DD3
Figure
= 2.5 V to 4.5 V; V
20).
Rev. 04 — 13 June 2008
Conditions
V
on bus
DD
= 3.0 V
SS1
t
su(RESL)
= V
SS2
= 0 V; V
[1]
[2]
[4]
[4]
t
w(RESL)
Min
40
20
20
300
-
0
1.3
0.6
100
0
20 + 0.1C
20 + 0.1C
-
0.6
0.6
0.6
-
1.3
DD1
to V
V
b
b
IL
DD3
Typ
66
34
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
34 x 128 pixel matrix driver
V
mgs476
LCD
PCF8531
9.0 V; T
Max
135
65
65
30
400
-
-
-
0.9
0.3
0.3
400
-
-
-
50
-
© NXP B.V. 2008. All rights reserved.
IL
and V
amb
= 40 C
IH
Unit
Hz
kHz
kHz
ns
kHz
ns
ns
pF
ns
, with an
32 of 44
s
s
s
s
s
s
s
s
s

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