PCF8531U NXP [NXP Semiconductors], PCF8531U Datasheet - Page 12

• Manufacturer Part Number: PCF8531U
• Description: 34 x 128 pixel matrix driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8531_4
Product data sheet
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] In the application, T2 must be left open-circuit.
If the on-chip oscillator is used, this input must be connected to V
If the internal V
If an external V
will be damaged.
If only the internal power-on reset is used, this input must be connected to V
V
V
connected together.
Serial data acknowledge for the I
fully I
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from
the SDACK pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up
resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that the PCF8531 will not be able to
create a valid logic 0 level during the acknowledge cycle. By splitting the SDA input from the SDACK output,
the device could be used in a mode that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the
system SDA line to guarantee a valid LOW level.
If ENR is connected to V
to V
In the application, this input must be connected to V
V
DD1
DD3
SS1
DD1
2
and V
is for the logic supply, V
must be connected together. If only one supply voltage is available, V
C-bus compatible. Having the acknowledge output separated from the serial data line is
.
SS2
LCD
must be connected together.
LCD
is used in the application, then pin V
generation is used, V
Rev. 04 — 13 June 2008
SS
, power-on reset is disabled; to enable power-on reset ENR must be connected
DD2
2
and V
C-bus. By connecting SDACK to SDA externally, the SDA line becomes
DD3
LCDOUT
are for the voltage multiplier. For split power supplies, V
, V
LCDIN
SS
.
LCDOUT
and V
LCDSENSE
must be left open-circuit, otherwise the chip
DD1
.
34 x 128 pixel matrix driver
must be connected together.
DD1
DD1
, V
.
DD2
PCF8531
© NXP B.V. 2008. All rights reserved.
and V
DD3
must be
DD2
12 of 44
and