PCF8531U NXP [NXP Semiconductors], PCF8531U Datasheet - Page 28

• Manufacturer Part Number: PCF8531U
• Description: 34 x 128 pixel matrix driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8531_4
Product data sheet
Fig 19. Master transmits to slave receiver; write mode
S 0 1 1 1 1 0
slave address
11.2 I
from PCF8531
S
A
acknowledge
0
This driver does not support ‘read’. The PCF8531 is a slave receiver. Therefore, it only
responds when R/W = 0 in the slave address byte.
Before any data is transmitted on the I
first. Two 7-bit slave addresses (011 1100 and 011 1101) are reserved for the PCF8531.
The least significant bit of the slave address is set by connecting the input SA0 to either
logic 0 (V
The I
The sequence is initiated with a START condition (S) from the I
followed by the slave address. All slaves with the corresponding address acknowledge in
parallel, all others ignore the I
command words follow, which define the status of the addressed slaves. A command
word consists of a control byte, which defines Co and RS, plus a data byte (see
and
The last control byte is tagged with a cleared most significant bit, the continuation bit Co.
The control and data bytes are also acknowledged by all addressed slaves on the bus.
After the last control byte, depending on the RS bit setting, either a series of display data
bytes or command data bytes may follow. If the RS bit was set to logic 1, these display
bytes are stored in the display RAM at the address specified by the data pointer.
The data pointer is automatically updated and the data is directed to the intended
PCF8531 device. If the RS bit of the last control byte was set to logic 0, these command
bytes will be decoded and the setting of the device will be changed according to the
received commands. The acknowledgement after each byte is made only by the
addressed PCF8531. At the end of the transmission, the I
condition (P).
R/W
2
0 A
Fig 18. Slave address and control byte
C-bus protocol
Table
Co
2
1
C-bus protocol is shown in
RS
S
SS
11).
0
control byte
) or logic 1 (V
1
from PCF8531
acknowledge
slave address
1
2n
A
1
0 bytes
Rev. 04 — 13 June 2008
DD
1
).
data byte
2
0
C-bus transfer. After acknowledgement, one or more
SA0
Figure
from PCF8531
acknowledge
R/W
2
C-bus, the device that must respond is addressed
18.
A
A
Co
0
RS
control byte
1 byte
Co RS
from PCF8531
acknowledge
2
C-bus master issues a STOP
A
34 x 128 pixel matrix driver
MSB . . . . . . . . . . . LSB
X
2
C-bus master, and is
control byte
data byte
X
n
0 bytes
X
PCF8531
© NXP B.V. 2008. All rights reserved.
from PCF8531
acknowledge
X
mgs475
A P
X
mgs474
Figure 19
X
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