CY7C1470V25-250AXC CYPRESS [Cypress Semiconductor], CY7C1470V25-250AXC Datasheet - Page 8

• Manufacturer Part Number: CY7C1470V25-250AXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05290 Rev. *E
(CE
counter is incremented. The correct BW (BW
CY7C1474V25, BW
CY7C1472V25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
Interleaved Burst Address Table
(MODE = Floating or V
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BW
2. Write is defined by WE and BW
3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles.During a Read cycle DQ
signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
OE is inactive or when the device is deselected, and DQ
1
Address
, CE
Parameter
A1,A0
First
00
01
10
11
2
, and CE
Operation
[1, 2, 3, 4, 5, 6, 7]
3
ZZREC
) and WE inputs are ignored and the burst
a,b,c,d
Address
Second
A1,A0
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
1
, CE
01
00
10
11
after the ZZ input returns LOW.
for CY7C1470V25 and BW
2
[a:d]
, and CE
DD
. See Write Cycle Description table for details.
)
Description
Address
A1,A0
Third
3
, must remain inactive
10
11
00
01
Next
None
None
External
External
Next
External
Next
None
Address
Used
a,b,c,d,e,f,g,h
s
= data when OE is active.
Address
Fourth
PRELIMINARY
A1,A0
11
10
01
00
CE
H
X
X
X
X
L
L
L
L
a,b
for
for
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
ZZ
L
L
L
L
L
L
L
L
L
Linear Burst Address Table (MODE = GND)
ADV/LD
DD
DD
Test Conditions
− 0.2V
− 0.2V
H
H
H
H
L
L
L
L
L
Address
A1,A0
First
00
01
10
11
x
WE
= L signifies at least one Byte Write Select is active, BW
X
X
H
X
H
X
X
L
L
BW
X
X
X
X
X
X
H
L
L
Address
Second
x
A1,A0
01
10
11
00
OE
X
X
H
H
X
X
X
L
L
CEN
2t
Min.
s
L
L
L
L
L
L
L
L
L
CYC
and DQP
Address
0
A1,A0
CY7C1470V25
CY7C1472V25
CY7C1474V25
Third
10
11
00
01
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
[a:d]
2t
2t
Max
120
= Three-state when
CYC
CYC
Data Out (Q)
Data Out (Q)
Page 8 of 27
Three-State
Three-State
Three-State
Three-State
Three-State
Data In (D)
Data In (D)
Address
Fourth
A1,A0
DQ
11
00
01
10
x
Unit
mA
ns
ns
ns
ns
= Valid