CY7C1470V25-250AXC CYPRESS [Cypress Semiconductor], CY7C1470V25-250AXC Datasheet - Page 7

• Manufacturer Part Number: CY7C1470V25-250AXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05290 Rev. *E
Introduction
Functional Overview
The
synchronous-pipelined Burst NoBL SRAMs designed specifi-
cally to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
Accesses can be initiated by asserting all three Chip Enables
(CE
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BW
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A Read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a Read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE is active LOW. After the first
clock of the Read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
Burst Read Accesses
The CY7C1470V25/CY7C1472V25/CY7C1474V25 have an
on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
CO
1
) is 3.0 ns (250-MHz device).
, CE
CY7C1470V25/CY7C1472V25/CY7C1474V25
3
2
are ALL asserted active, (3) the Write Enable input
, CE
3
) active at the rising edge of the clock. If Clock
1
, CE
[x]
2
can be used to
, CE
PRELIMINARY
3
) and an
1
, CE
are
2
,
A1 in the burst sequence, and will wrap-around when incre-
mented sufficiently. A HIGH input on ADV/LD will increment
the internal burst counter regardless of the state of chip
enables inputs or WE. WE is latched at the beginning of a burst
cycle. Therefore, the type of access (Read or Write) is
maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
is asserted LOW. The address presented to the address inputs
is loaded into the Address Register. The Write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQ
DQ
CY7C1472V25). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DQP
(DQ
DQ
CY7C1472V25) (or a subset for Byte Write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the Write is complete.
The data written during the Write operation is controlled by BW
(BW
CY7C1470V25 and BW
CY7C1470V25/CY7C1472V25/CY7C1474V25 provides Byte
Write capability that is described in the Write Cycle Description
table. Asserting the Write Enable input (WE) with the selected
Byte Write Select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the Write
operations. Byte Write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple Byte Write operations.
Because the CY7C1470V25/CY7C1472V25/CY7C1474V25
are common I/O devices, data should not be driven into the
device while the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQ and
DQP (DQ
DQ
CY7C1472V25) inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ and DQP (DQ
DQP
CY7C1470V25 and DQ
automatically three-stated during the data portion of a Write
cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1470V25/CY7C1472V25/CY7C1474V25 has an
on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four Write operations
without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the Chip Enables
a,b,c,d
a,b,c,d
a,b,c,d
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
3
/DQP
/DQP
/DQP
are ALL asserted active, and (3) the Write signal WE
a,b,c,d,e,f,g,h
a,b,c,d
a,b,c,d
a,b,c,d
/DQP
/DQP
for CY7C1474V25, DQ
for
for CY7C1470V25 and DQ
for CY7C1470V25 and DQ
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
for CY7C1470V25 & DQ
/DQP
a,b
a,b
CY7C1474V25,
/DQP
a,b,c,d,e,f,g,h
for CY7C1472V25) signals. The
a,b
for CY7C1472V25) are
CY7C1470V25
CY7C1472V25
CY7C1474V25
for
for
for CY7C1474V25,
a,b,c,d
CY7C1474V25,
CY7C1474V25,
BW
/DQP
a,b
a,b
a,b
Page 7 of 27
a,b,c,d
/DQP
a,b,c,d,e,f,g,h
/DQP
/DQP
a,b,c,d
1
a,b
, CE
a,b
a,b
for
for
for
for
for
2
,
/