VSC8140QR VITESSE [Vitesse Semiconductor Corporation], VSC8140QR Datasheet - Page 10

• Manufacturer Part Number: VSC8140QR
• Description: 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

Transceiver with Integrated Clock Generator
2.48832Gb/s 16:1 SONET/SDH
Page 10
Transmitter High-Speed Data and Clock Outputs
designed to drive a 50
the load between true and complement outputs (see Figure 13). No connection to a termination voltage is
required. The output driver is back terminated to 50 on-chip, providing a snubbing of any reflections. If used
single-ended, the high-speed output driver must still be terminated differentially at the load with a 100 resistor
between true and complement outputs.
necting the power pins VEEP_CLK and VEE_PWRDN to the V
Reference Clock Inputs
Off-chip termination of these inputs is required (see Figure 14).
where this does not hold, direct DC connection is possible. All serial clock inputs have the same circuit topol-
ogy, as shown in Figure 14. If the input signal is driven differentially and DC-coupled to the part, the mid-point
of the input signal swing should be centered about the input common-mode voltage V
maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user pro-
vides an external reference voltage. The external reference should have a nominal value equivalent to the com-
mon-mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate.
In order to save power, the high-speed transmit clock output (TXCLKOUT) can be powered down by con-
The high-speed data and clock output drivers (TXOUT and TXCLKOUT) consist of a differential pair
The incoming low-speed reference clock inputs are received by differential LVPECL inputs REFCLK± .
In most situations these inputs will have high transition density and little DC offset. However, in cases
Figure 14: AC Termination of Low-Speed LVPECL REFCLK and LPTIMCLK Inputs
Z
O
Z
O
V
V
V
V
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
C
CC
EE
C
CC
EE
IN
IN
transmission line. The transmission line should be terminated with a 100
R1
R2
R1
R2
VITESSE
SEMICONDUCTOR CORPORATION
VITESSE SEMICONDUCTOR CORPORATION
Chip Boundary
V
V
CC
EE
= 3.3V
= 0V
CC
supply instead of to V
R1||R2 = Z
V
CC
R2 + V
R1+R2
C
for AC operation
IN
CM
o
EE
, R1 = 83
TYP = 100nF
EE
.
and not exceed the
R1
= V
VSC8140
Data Sheet
G52251-0, Rev. 4.0
BIAS
R2 =125
resistor at
9/6/00