MBM29F400BC-55 FUJITSU [Fujitsu Component Limited.], MBM29F400BC-55 Datasheet - Page 21

• Manufacturer Part Number: MBM29F400BC-55
• Description: 4M (512K X 8/256K X 16) BIT
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Power-Up Write Inhibit
To avoid initiation of a write cycle during V
than 3.2 V (typically 3.7 V). If V
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE = V
must be a logical zero while OE is a logical one.
Power-up of the device with WE = CE = V
The internal state machine is automatically reset to the read mode on power-up.
CC
CC
Write Inhibit
level is greater than V
MBM29F400TC
LKO
CC
. It is the users responsibility to ensure that the control pins are logically correct
< V
LKO
, the command register is disabled and all internal program/erase circuits
CC
is above 3.2 V.
CC
IL
and OE = V
power-up and power-down, a write cycle is locked out for V
-55/-70/-90
IL
, CE = V
IH
will not accept commands on the rising edge of WE.
IH
, or WE = V
/MBM29F400BC
IH
. To initiate a write cycle CE and WE
-55/-70/-90
CC
less
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