MBM29F400BC-55 FUJITSU [Fujitsu Component Limited.], MBM29F400BC-55 Datasheet - Page 18

• Manufacturer Part Number: MBM29F400BC-55
• Description: 4M (512K X 8/256K X 16) BIT
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

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MBM29F400TC
DQ
Data Polling
DQ
Toggle Bit I
DQ
Exceeded Timing Limits
The MBM29F400TC/BC device feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device
will produce the complement of the data last written to DQ
Algorithm, an attempt to read the device will produce the true data last written to DQ
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ
for Data Polling (DQ
For Programing, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29F400TC/BC data pins (DQ
enable (OE) is asserted low. This means that the device is driving status information on DQ
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation
and DQ
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out (See Table 8).
See Figure 9 for the Data Polling timing specifications and diagrams.
The MBM29F400TC/BC also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ
cycle is completed, DQ
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit l will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
cause DQ
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
DQ
these conditions DQ
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
7
6
5
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
7
has a valid data, the data outputs on DQ
6
to toggle.
7
5
) is shown in Figure 21.
will produce a “1”. This is a failure condition which indicates that the program or erase
6
will stop toggling and valid data will be read on the next successive attempts. During
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
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6
/MBM29F400BC
to toggle. In addition, an Erase Suspend/Resume command will
0
to DQ
6
may be still invalid. The valid data on DQ
7
. Upon completion of the Embedded Program
7
) may change asynchronously while the output
7
output. Upon completion of the
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. During the Embedded
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output. The flowchart
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at one instant of
0
to DQ
7
will
7