C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 215

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Interrupt System
C509-L
7.4
How Interrupts are Handled
The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during
the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceeding
cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate
service routine, provided this hardware-generated LCALL is not blocked by any of the following
conditions:
1. An interrupt of equal or higher priority is already in progress.
2. The current (polling) cycle is not in the final cycle of the instruction in progress.
3. The instruction in progress is RETI or any write access to registers IEN0, IEN1, IEN2, IEN3,
EICC1, IP1 or IP0.
Any of these three conditions will block the generation of the LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress is completed before vectoring to any service
routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to
registers IEN0, IEN1, IEN2, IEN3, EICC1, IP1 or IP0, then at least one more instruction will be
executed before any interrupt is vectored to; this delay guarantees that changes of the interrupt
status can be observed by the CPU.
The polling cycle is repeated with each machine cycle and the values polled are the values that
were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is active but not
being responded to for one of the conditions already mentioned, or if the flag is no longer active
when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the
fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle
interrogates only the pending interrupt requests.
The polling cycle/LCALL sequence is illustrated in figure 7-5.
C1
C2
C3
C4
C5
S5P2
Interrupts
Long Call to Interrupt
Interrupt
Interrupt
are polled
Vector Address
Routine
is latched
MCT01859
Figure 7-5
Interrupt Response Timing Diagram
Semiconductor Group
7-19
1997-10-01