C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 154

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

The arithmetic control register ARCON contains control flags and the shift counter of the MDU. It
triggers a shift or a normalize operation in register MD0 to MD3 when being written to.
Special Function Register ARCON (Address EF H )
Bit
MDEF
MDOV
SLR
SC.4 - SC.0
Semiconductor Group
Bit No.
EF H
MDEF MDOV
MSB
7
Function
Error flag
Indicates an improperly performed operation. MDEF is set by hardware
when an operation is retriggered by a write access to MDx before the first
operation has been completed. MDEF is automatically cleared after being
read.
Overflow flag
Exclusively controlled by hardware. MDOV is set by following events:
Shift direction bit
When set, shift right is performed. SLR = 0 selects shift left operation.
Shift counter bits
When preset with 00000 B , normalizing is selected. After operation SC.0 to
SC.4 contain the number of normalizing shifts performed. When set with a
value
determined by the count written to SC.0 to SC.4.
– division by zero
– multiplication with a result greater than FFFF H .
6
0, shift operation is started. The number of shifts performed is
SLR
5
SC.4
4
6-76
SC.3
3
On-Chip Peripheral Components
SC.2
2
SC.1
1
Reset Value : 0XXXXXXX B
SC.0
LSB
0
ARCON
1997-10-01
C509-L