AD5410ACPZ AD [Analog Devices], AD5410ACPZ Datasheet - Page 24

• Manufacturer Part Number: AD5410ACPZ
• Description: Single Channel, 16-Bit, Serial Input, Current Source DAC
• Manufacturer: AD [Analog Devices]

AD5410/AD5420
DIGITAL SLEW RATE CONTROL
The Slew Rate Control feature of the AD5410/AD5420 allows
the user to control the rate at which the output current changes.
With the slew rate control feature disabled the output currrent
will change at a rate limited by the output drive circuitry and
the attached load. If the user wishes to reduce the slew rate this
can be achieved by enabling the slew rate control feature.With
the feature enabled via the SREN bit of the CONTROL register,
(See Table 13) the output, instead of slewing directly between
two values, will step digitally at a rate defined by two
parameters accessible via the CONTROL register as shown in
Table 13. The parameters are SR CLOCK and SR STEP. SR
CLOCK defines the rate at which the digital slew will be
updated SR STEP defines by how much the output value will
change at each update. Together both parameters define the rate
of change of the output current.Table 20 and Table 21 outline
the range of values for both the SR CLOCK and SR STEP
parameters.
Table 20. Slew Rate Update Clock Options
SR CLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Update Clock Frequency (Hz)
257732
198413
152439
131579
115741
69444
37594
25773
20161
16026
10288
8278
6897
5525
4237
3300
Rev. PrE | Page 24 of 30
Table 21. Slew Rate Step Size Options
The time it will take for the output current to slew over a given
output range can be expressed as follows.
Where:
Slew Time is expressed in seconds
Output Change is expressed in Amps
When the slew rate control feature is enabled, all output
changes will change at the programmed slew rate, i.e. if the
CLEAR pin is asserted the output will slew to the clear value at
the programmed slew rate. The output can be halted at its
current value with a write to the CONTROL register. To avoid
halting the output slew, the SLEW ACTIVE bit can be read to
check that the slew has completed before writing to the
AD5410/AD5420 registers. See Table 18. The update clock
frequency for any given value will be the same for all output
ranges. The step size however will vary across output ranges for
a given value of step size as the LSB size will be different for
each output range. Table 22 shows the range of programmable
slew times for a full-scale change on any of the output ranges.
The values were obtained using the Slew Time equation above.
SlewTime
SR STEP
000
001
010
011
100
101
110
111
=
StepSize
Preliminary Technical Data
×
UpdateCloc
AD5410 Step
Size (LSBs)
OutputChan
1
⁄
⅛
¼
½
1
2
4
8
16
kFrequency
ge
AD5420 Step
Size (LSBs)
128
×
16
32
64
1
2
4
8
LSBSize