AD5410ACPZ AD [Analog Devices], AD5410ACPZ Datasheet
AD5410ACPZ
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AD5410ACPZ Summary of contents
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Preliminary Technical Data FEATURES 12/16-Bit Resolution and Monotonicity Current Output Ranges: 4–20mA, 0–20mA or 0–24mA 0.1% typ Total Unadjusted Error (TUE) 5ppm/°C Output Drift Flexible Serial Digital Interface On-Chip Output Fault Detection On-Chip Reference (10 ppm/°C Max) Asynchronous CLEAR Function ...
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AD5410/AD5420 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 AC Performance Characteristics ................................................ 6 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 ...
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Preliminary Technical Data FUNCTIONAL BLOCK DIAGRAM SELECT AD5410/AD5420 CLEA R SELECT CLEA R INPUT SHIFT LATCH REGISTER SCLK AND SDIN CONTROL SDO LOGIC POWER ON RESET DGND* *LFCSP Package CAP1* CAP2* CC 12/16-Bit 16 / DAC VREF ...
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AD5410/AD5420 SPECIFICATIONS 10.8V to 40V/60V , AGND = DGND = 0 V, REFIN external all specifications range unless otherwise noted. MIN MAX Table 2. Parameter ...
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Preliminary Technical Data Parameter Input Current Pin Capacitance DIGITAL OUTPUTS 3 SDO V , Output Low Voltage Output High Voltage OH High Impedance Leakage Current High Impedance Output Capacitance FAULT V , Output Low Voltage OL V ...
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AD5410/AD5420 AC PERFORMANCE CHARACTERISTICS 10.8V to 40V/60V , AGND = DGND = 0 V, REFIN external all specifications range unless otherwise noted. MIN MAX Table ...
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Preliminary Technical Data TIMING CHARACTERISTICS 10.8V to 40V/60V , AGND = DGND = 0 V, REFIN external all specifications range unless otherwise noted. MIN MAX ...
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AD5410/AD5420 SCLK LATCH SDIN CLEAR OUTPUT SCLK LATCH SDIN DB23 INPUT WORD SPECIFIES REGISTER TO BE READ SDO UNDEFINED DATA SCLK 1 2 LATCH SDIN DB23 INPUT WORD FOR DAC ...
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted. A Transient currents 100 mA do not cause SCR latch-up. Table 5. Parameter Rating AV to AGND, DGND −0.3V to 60V AGND, ...
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Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND FAULT 3 GND 4 GND 5 CLEAR 6 LATCH 7 SCLK 8 SDIN 9 SDO 10 AGND 11 GND 12 Figure 5. TSSOP Pin Configuration Table 6. ...
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Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. Integral Non Linearity vs. Code Figure 8.Differential Non Linearity vs. Code Figure 9. Total Unadjusted Error vs. Code Figure 10. Integral Non Linearity vs. Temperature Figure 11. Differential Non Linearity vs. Temperature ...
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AD5410/AD5420 Figure 13. Differential Non Linearity vs. Supply Voltage Figure 14. Integral Non Linearity vs. Reference Voltage Figure 15. Differential Non Linearity vs. Reference Voltage Preliminary Technical Data Figure 16. Total Unadjusted Error vs. Reference Voltage Figure 17. Total Unadjusted ...
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Preliminary Technical Data Figure 19. Gain Error vs. Temperature Figure 20. Voltage Compliance vs. Temperature Figure 23. DI vs.Logic Input Voltage CC Figure 21. I Figure 22. I OUT Figure 24. AI Rev. PrE | Page AD5410/AD5420 ...
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AD5410/AD5420 Figure 25. DV Output Voltage vs Figure 26. Refout Turn-on Transient Figure 27. Refout Output Noise (0.1Hz to 10Hz Bandwidth) Load Current CC Rev. PrE | Page Preliminary Technical Data Figure 28. Refout Output ...
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Preliminary Technical Data Figure 31. Refout Histogram of Thermal Hysteresis Figure 32. Refout Voltage vs. Load Current Rev. PrE | Page AD5410/AD5420 ...
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AD5410/AD5420 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity (INL measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A ...
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AD5410/AD5420 THEORY OF OPERATION The AD5410/AD5420 is a precision digital to current loop output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop ...
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AD5410/AD5420 Table 7. The 24 bit word is unconditionally latched on the rising edge of LATCH. Data will continue to be clocked in irrespective of the state of LATCH, on the rising edge of LATCH the data that is present ...
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Preliminary Technical Data Table 7. Input Shift Register Format MSB D23 D22 D21 D20 D19 D18 D17 ADDRESS WORD Table 8. Address Word Functions Address Function Word 00000000 No Operation (NOP) 00000001 DATA Register 00000010 Readback register value as per ...
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AD5410/AD5420 Daisy-Chain Operation For systems that contain several devices, the SDO pin can be used to daisy chain several devices together as shown in Figure 35. This daisy-chain mode can be useful in system diagnostics and in reducing the number ...
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Preliminary Technical Data POWER-UP STATE On power-up of the AD5410/AD5420, the power-on-reset circuit ensures that all registers are loaded with zero-code, as such the output will be disabled (tri-state). TRANSFER FUNCTION For the 0 to 20mA 24mA and ...
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AD5410/AD5420 RESET REGISTER The RESET register is addressed by setting the control word of the input shift register to 0x56. The data to be written to the RESET register is entered in positions D15 shown in Table ...
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Preliminary Technical Data FEATURES FAULT ALERT The AD5410/AD5420 is equipped with a FAULT pin, this is an open-drain output allowing several AD5410/AD5420 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced ...
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AD5410/AD5420 DIGITAL SLEW RATE CONTROL The Slew Rate Control feature of the AD5410/AD5420 allows the user to control the rate at which the output current changes. With the slew rate control feature disabled the output currrent will change at a ...
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Preliminary Technical Data Table 22. Programmable Slew Time values in seconds for a full scale change on any output range 0.25 0.13 257732 198413 0.33 0.17 152439 0.43 0.21 0.50 0.25 131579 0.57 0.28 115741 69444 0.9 0.47 ...
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AD5410/AD5420 APPLICATIONS INFORMATION DRIVING INDUCTIVE LOADS When driving inductive or poorly defined loads connect a 0.01µF capacitor between I and GND. This will ensure OUT stability with loads beyond 50mH. There is no maximum capacitance limit. The capacitive component of ...
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Preliminary Technical Data and a latch signal. The AD5410/AD5420 require a 24-bit data- word with data valid on the rising edge of SCLK. For all interfaces, the DAC output update is initiated on the rising edge of LATCH. The contents ...
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... BSC PLANE 0.10 COPLANARITY Figure 43. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] 6.00 BSC SQ PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Resolution AD5410AREZ 12 Bits AD5410ACPZ 12 Bits AD5420AREZ 16 Bits AD5420ACPZ 16 Bits 13 4.50 4.40 4.30 6.40 BSC 12 1.05 1.00 8° 0.80 0° 0.20 0.30 0.09 0.19 COMPLIANT TO JEDEC STANDARDS MO-153-ADT ...
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Preliminary Technical Data Rev. PrE | Page AD5410/AD5420 ...
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AD5410/AD5420 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07027-0-5/08(PrE) Preliminary Technical Data Rev. PrE | Page ...