HSC-INTERFACEBOARD AD [Analog Devices], HSC-INTERFACEBOARD Datasheet - Page 4

• Manufacturer Part Number: HSC-INTERFACEBOARD
• Description: 1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
AD7470/AD7472
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
Specifications subject to change without notice.
CLK
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/Space ratio for the CLK input is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of CONVST.
t
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
t
CONVERT
WAKEUP
1
2
3
4
5
6
7
8
9
10
Figure 1.
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
2
7
3
4
4
5
is 35 ns max @ +125°C.
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
2
AD7470
10
30
436.42
1
10
10
30
0
0
20
15
8
0
135
100
Limit at T
Figure 1. Load Circuit for Digital Output Timing Specifications
MIN
, T
1
(V
MAX
DD
AD7472
10
26
531.66
1
10
10
30
0
0
20
15
8
0
135
100
= +2.7 V to +5.25 V, REF IN = 2.5 V; T
TO OUTPUT
PIN
50pF
C
L
200 A
200 A
–4–
Units
kHz min
MHz max
ns min
µs max
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
I
I
OL
OH
A
= T
+1.6V
7
, quoted in the timing characteristics is the true bus relinquish
MIN
Description
t
Wake-Up Time
CONVST Pulsewidth
CONVST to BUSY Delay, V
CONVST to BUSY Delay, V
BUSY to CS Setup Time
CS to RD Setup Time
RD Pulsewidth
Data Access Time After Falling Edge of RD
Bus Relinquish Time After Rising Edge of RD
CS to RD Hold Time
Acquisition Time
Quiet Time
to T
CLK
MAX
= 1/f
DD
, unless otherwise noted.)
) and timed from a voltage level of 1.6 V. See
CLK IN
DD
DD
= 5 V
= 3 V
REV. A