HSC-INTERFACEBOARD AD [Analog Devices], HSC-INTERFACEBOARD Datasheet - Page 15

• Manufacturer Part Number: HSC-INTERFACEBOARD
• Description: 1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
• Manufacturer: AD [Analog Devices]

control line is actually three memory select lines. Internal
ADDR
as chip selects. The DMAR
setup as the interrupt to signal end of conversion. The rest of
the interface is standard handshaking operation.
AD7470/AD7472 to TMS320C25 Interface
Figure 28 shows an interface between the AD7470/AD7472
and the TMS320C25. The CONVST signal can be applied
from the TMS320C25 or from an external source. The BUSY
line interrupts the digital signal processor when conversion is
completed. The TMS320C25 does not have a separate RD
output to drive the AD7470/AD7472 RD input directly. This
has to be generated from the processor STRB and R/W outputs
with the addition of some glue logic. The RD signal is OR-gated
with the MSC signal to provide the WAIT state required in the
read cycle for correct interface timing. The following instruction
is used to read the conversion from the AD7470/AD7472:
where D is Data Memory address and the ADC is the AD7470/
AD7472 address. The read operation must not be attempted
during conversion.
REV. A
ADSP-21065L*
TMS320C25*
ADDR
25–24
DMD0–DMD15
Figure 28. Interfacing to the TMS320C25
0
Figure 27. Interfacing to ADSP-21065L
–ADDR
are decoded into MS
A0–A15
D0–D31
READY
DMAR
STRB
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
MSC
MS
R/W
RD
IS
23
X
1
ADDRESS BUS
ADDRESS BUS
IN D,ADC
DECODER
ADDRESS
DECODER
DATA BUS
ADDRESS
ADDRESS
DATA BUS
LATCH
1
(DMA Request 1) is used in this
ADDRESS
BUS
3-0
, these lines are then asserted
CS
BUSY
RD
CS
BUSY
RD
DB0–DB9
(DB11)
DB0–DB9
(DB11)
AD7472*
AD7470/
AD7472*
AD7470/
OPTIONAL
OPTIONAL
CONVST
CONVST
–15–
AD7470/AD7472 to PIC17C4x Interface
Figure 29 shows a typical parallel interface between the AD7470/
AD7472 and PIC17C42/43/44. The microcontroller sees the
A/D as another memory device with its own specific memory
address on the memory map. The CONVST signal can either be
controlled by the microcontroller or an external source. The
BUSY signal provides an interrupt request to the microcontroller
when a conversion ends. The INT pin on the PIC17C42/43/44
must be configured to be active on the negative edge. PORTC
and PORTD of the microcontroller are bidirectional and used
to address the AD7470/AD7472 and also to read in the 10-bit
(AD7470) or 12-bit (AD7472) data. The OE pin on the PIC
can be used to enable the output buffers on the AD7470/AD7472
and preform a read operation.
AD7470/AD7472 to 80C186 Interface
Figure 30 shows the AD7470/AD7472 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. (The AD7470/AD7472
occupies one of these I/O spaces.) Each data transfer consumes
two bus cycles, one cycle to fetch data and the other to store
data.
After the AD7470/AD7472 has finished conversion, the BUSY
line generates a DMA request to Channel 1 (DRQ1). As a result
of the interrupt, the processor performs a DMA READ opera-
tion which also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request will be serviced before the completion of the next con-
version. This configuration can be used with 6 MHz and 8 MHz
80C186 processors.
PIC17C4x*
80C186*
AD0–AD15
AD0–AD15
A16–A19
DRQ1
Figure 29. Interfacing to the PIC17C4x
ALE
ALE
INT
OE
Figure 30. Interfacing to the 80C186
RD
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS/DATA BUS
ADDRESS
DECODER
Q
ADDRESS
LATCH
R
S
ADDRESS
LATCH
ADDRESS
BUS
AD7470/AD7472
ADDRESS
DECODER
DATA BUS
DB0–DB9
(DB11)
CS
RD
BUSY
CS
BUSY
RD
DB0–DB9
(DB11)
AD7472*
AD7472*
AD7470/
AD7470/
OPTIONAL
OPTIONAL
CONVST
CONVST