UPD72042BGT NEC [NEC], UPD72042BGT Datasheet - Page 24

• Manufacturer Part Number: UPD72042BGT
• Description: LSI DEVICE FOR Inter Equipment Bus (IEBus) PROTOCOL CONTROL
• Manufacturer: NEC [NEC]

(2) Data read mode
24
(3) Data write mode
Caution When the C/D pin is set high in data read mode, the serial clock counter is reset. Therefore, the
Caution Register overwrite is started immediately after the eighth clock rising edge. All registers other
When the C/D pin is set low after register read is selected in control mode, the data read mode is set. In data
read mode, the data in a read register is read on the SO pin upon detecting the falling edge of the SCK pin.
When the C/D pin is set low after register write has been selected in control mode, data write mode is set. In
data write mode, data for a write register is applied to the SI pin at the rising edge of the SCK pin.
Serial clock counter
Serial clock counter
remaining bits of the byte cannot be read; at the next falling edge, read is performed starting from
the next byte in the case of RBF, or from the first bit for other registers.
than TBF are overwritten on the eighth clock rising edge. (Data of less than eight clock periods
is ignored.)
reset pointer
reset pointer
State
State
SCK
C/D
SO
SCK
C/D
SI
SO
SI
“1”
“1”
(selection of register read)
(selection of register write)
Control mode
Control mode
1
0
Data Sheet S13990EJ3V0DS
A0 A1 A2 A3
A0 A1 A2 A3
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Data read mode
Data write mode
PD72042B