UPD30121 NEC [NEC], UPD30121 Datasheet - Page 56

• Manufacturer Part Number: UPD30121
• Description: VR4121TM 64-/32-BIT MICROPROCESSOR
• Manufacturer: NEC [NEC]

56
Address setup time (to command signal )
Command signal low-level width
Address hold time (from command signal )
Command signal recovery time
IOCHRDY sampling start time
Command signal
IOCHRDY hold time (from command signal )
Data output setup time (to command signal )
Data output hold time (from command signal )
MEMCS16#/IOCS16# sampling start time
MEMCS16#/IOCS16# hold time (from command
signal )
Data input setup time
Data input hold time
Remarks 1. Do not set CLKSEL (2:0) signal
(14) High-speed system bus parameter (IOCHRDY) (1/2)
Notes 1. With the V
CLKSEL2
Signal
1
1
1
1
0
0
0
0
Note 1
2. The values of N and M are set by using the WLCD/M (0:2) bits of the BCUSPEEDREG register.
2. Do not set CLKSEL (2:0) signal
system bus interface.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL1
= 111.
= 110, 101 with 131 MHz model.
Signal
delay time from IOCHRDY
1
1
0
0
1
1
0
0
Parameter
R
4121, the MEMW# and MEMR# signals are called the command signals for the high-speed
CLKSEL0
Notes 1, 2
Notes 1, 2
Signal
1
0
1
0
1
0
1
0
Note 2
Notes 1, 2
Note 1
Note 1
Note 1
T (ns)
RFU
Note 1
Notes 1, 2
35
33
30
33
30
33
38
Data Sheet U14691EJ1V0DS00
Symbol
t
t
t
t
t
t
t
t
t
t
AVSV1
t
RHCH
CHDV
AVCL
CLCH
CHAV
CHCL
CHRL
DVCL
CHSV
t
t
CLR
DS
DH
WLCD/M2
Bit
0
0
0
0
1
1
1
1
Condition
WLCD/M1
Bit
0
0
1
1
0
0
1
1
T
WLCD/M0
T
2
T
(N + M)
Bit
(N + 1)
T
0
1
0
1
0
1
0
1
T
MIN.
N
25
25
0
0
15
0
0
5
N – 44
M
29
29
29
(TClock)
T
N
8
7
6
5
4
3
2
1
(N + M) + 29
MAX.
(TClock)
M
8
7
6
5
4
3
2
2
PD30121
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns