mu9c4k64-90tdi Music Semiconductors, Inc., mu9c4k64-90tdi Datasheet
mu9c4k64-90tdi
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mu9c4k64-90tdi Summary of contents
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MU9C Routing CoProcessor (RCP) Family APPLICATION BENEFITS • Longest Prefix Match searches of IPv4 addresses • 28 Million IPv4 packets per second supports Ethernet or 7 OC-48 ATM ports at wire speed • Longest Prefix Match ...
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MU9C Routing CoProcessor (RCP) Family GENERAL DESCRIPTION The MU9C RCP family consists of 4K and 8K x 64-bit Routing CoProcessors (RCPs) with a 32-bit wide data interface and a 32-bit ternary compare instruction. The device is designed for use in ...
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Packet Stream Packet Stream ontrol C ontrol PIN DESCRIPTIONS Note: Signal names that start with a slash ("/") are active LOW. All signals are 3.3V CMOS level. ...
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... AC4 AC4 48 48 VDD VDD 47 47 VDDCORE # VDDCORE # AC3 AC3 46 46 AC2 AC2 45 45 AC1 AC1 44 44 AC0 AC0 43 43 VDDCORE # VDDCORE # 42 42 VSS VSS 41 41 TDO TDO 40 40 TDI TDI MU9C4K64 # See Pin Description for VDDCORE Rev. 8.10 ...
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Pin Descriptions PA3-0 (Page Address, Output) The PA3-0 lines convey Page Address information. When the /OE input is HIGH, the PA3-0 outputs are in their high-impedance state; when /OE is LOW the PA3-0 lines carry the Page Address value held ...
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MU9C Routing CoProcessor (RCP) Family /FF (Full Flag, Output) The /FF output indicates when all the memory locations have their Validity bits set valid (LOW). When there is at least one location with its Validity bit set HIGH, the /FF ...
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Functional Description FUNCTIONAL DESCRIPTION Data is read from and written to the MU9C RCP through the DQ31-0 lines. The Control bus, which is comprised of Chip Enable (/E), two Chip Selects (/CS1, /CS2), Write Enable (/W), Output Enable (/OE), Validity ...
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MU9C Routing CoProcessor (RCP) Family lowest-priority device provides a system Match flag. If the delay through the daisy chain is unacceptable, the /OE input can be used by external priority-resolution circuitry to enable the highest-priority responder in the system. The ...
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Operational Characteristics The instruction is persistent, so that all subsequent data transactions will be executed according to the control state held in the Instruction register. The results of a Comparison cycle can be read back from the Status register, and ...
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MU9C Routing CoProcessor (RCP) Family Active Address Interface PA:AA Bus The Active Address interface PA:AA bus carries the currently active address. The address source depends on the most recent control state that caused it to change. The possible address sources ...
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Register Descriptions PA:AA Bus and the Match Flags The Match flags /MF and /MM reflect the results of the most recent Comparison cycle. During a Comparison cycle, they do not change until after /E has gone HIGH after which they ...
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MU9C Routing CoProcessor (RCP) Family Status Register The 32-bit Status register holds the results of the most recent control state that caused the PA:AA lines to change intended for use in Software Control mode where results of an ...
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Register Descriptions The conditions of the Device Select register, the /CS1 and /CS2 lines are sampled at the time of the falling edge of / particular MU9C RCP within a system, that CAM will be selected under the ...
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MU9C Routing CoProcessor (RCP) Family Full Cascading The Full flag is set LOW in a particular MU9C RCP if the /FI line is LOW, and that device is full. During a Write cycle, the Full flag will not change until ...
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Register Descriptions External Prioritization For systems where the propagation delay associated with the Match Flag daisy chain is unacceptable, the MU9C RCP supports external prioritization. Using external prioritization, each /MF output is fed prioritizing circuit ...
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... JTAG instructions. The least significant bit is clocked in first. The JTAG instructions are as follows: JTAG Function EXTEST RESERVED RESERVED CLAMP IDCODE INTEST SAMPLE/PRELOAD BYPASS The MU9C4K64 IDCode is: MU9C8K64 IDCode is: XAC08133H (X is the four-bit revision code) BSDL files are available; Semiconductors website or contact MUSIC Technical Support. Instruction ...
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Control State Overview CONTROL STATE OVERVIEW Table 1: Control State Overview AC Bus /W = LOW Register Read/Write (32-bit operations) xxx xxx 000 011 NOP xxx nnn 000 100 WR AR {MRnnn} xxx nnn 000 110 WR FR {MRnnn} xxx ...
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MU9C Routing CoProcessor (RCP) Family CONTROL STATE DESCRIPTIONS REGISTER READ/WRITE Control State: No Operation Mnemonic: NOP Binary Binary Op-Code: XXX XXX 000 011 /W: LOW /AV: HIGH PA:AA: n/c Scope: n/a Description: No operation. The device performs no operation during ...
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Control State Descriptions Control State: Read Comparand Register Mnemonic: RDs CR Binary Op-Code: 0 XXX XXX 000 101 /W: HIGH /AV: HIGH PA:AA: n/c Scope: S Description: Reads bits 31-0 (DSC LOW) or 63-32 (DSC HIGH) of the Comparand register ...
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MU9C Routing CoProcessor (RCP) Family Control State: Indirect Write at Address; Increment Address Register Mnemonic: WRs[AR]+{MRnnn} Binary Op-Code: XXX nnn 100 110 /W: LOW /AV: HIGH PA:AA: aaa Scope: AS Description: Writes data from the DQ31-0 bus to bits 31-0 ...
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Control State Descriptions Control State: Write at Next Free Address Mnemonic: WRs[NFA]{MRnnn} Binary Op-Code: XXX nnn 000 001 /W: LOW /AV: HIGH PA:AA: NFA Scope: NFD Description: Writes data from the DQ31-0 bus to bits 31-0 (DSC LOW) or 63-32 ...
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MU9C Routing CoProcessor (RCP) Family Control State: Move Data from Highest-Priority Matching Location to Comparand Register Mnemonic: MOV CR,[HPM]{MRnnn} Binary Op-Code: XXX nnn 001 110 /W: HIGH /AV: HIGH PA:AA: HPMA Scope: HPD Description: Moves data from the Highest-Priority Match ...
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Control State Descriptions VALIDITY BIT CONTROL Control State: Set Valid Indirect Mnemonic: SET V@[AR] Binary Op-Code: XXX XXX 100 000 /W: LOW /AV: HIGH PA:AA: aaa Scope: AS Description: Set the Validity bit LOW at the location pointed to by ...
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MU9C Routing CoProcessor (RCP) Family Table 2: Reset Conditions Resource Memory Array Comparand Register Mask Registers 1-7 Address Register Instruction Register Next Free Address Register Device Select Register DS31-4 Reserved DS8 SELEN DS7-4 Reserved DS3-0 Device Select Status Register SR31 ...
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Control State Descriptions Table 4: Status Register Bit Assignments Names Bit(s) 31 Reserved 30 /MF 29 /MM 28 /FF 27:26 Reserved 25:24 Active Address Type 23:20 Reserved 19:16 Page Address PA3-0 15:13 Reserved 12:0 Active Address AA12-0 Table 5: Next ...
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... Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. All voltages referenced to VSS. Min. Typical Max. 3.0 3.3 3.6 2 0.3 -0.3 0.8 Commercial 0 Industrial -40 Min. Typical MU9C4K64 200 -35 470 MU9C8K64 -40 410 -50 320 -70 225 -90 180 2 2.4 Others -2 Internal 6 9 Pull-Ups -10 Max ...
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... Test Load A C1 (includes jig) Test Load B Rev. 8.10 To Device To Device Under Test Under Test R2 R2 Figure 5: AC Test Load POINT POINT Figure 6: Input Signal Waveform MU9C4K64 MU9C8K64 3.3 635 702 MU9C Routing CoProcessor (RCP) Family ...
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MU9C Routing CoProcessor (RCP) Family SWITCHING CHARACTERISTICS No. Symbol Parameter 1a tELEL Chip Enable Cycle Time (Other Cycles) 1b tELEL Chip Enable Cycle Time (Compare Cycles) 2a tELEH Chip Enable LOW Pulse Width (Other Cycles) 2b tELEH Chip Enable LOW ...
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Timing Diagrams TIMING DIAGRAMS / /AV /AV AC Bus AC Bus D Q 31-0, / 31-0, / ...
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MU9C Routing CoProcessor (RCP) Family / ...
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Packages PACKAGES 100-pin Dim. Dim. Dim. LQFP Min. 0.05 1.35 0.22 Max. 0.15 1.45 0. 128-pin Dim. Dim. Dim. LQFP Min. 0.05 1.35 0.17 Max. 0.15 ...
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... ORDERING INFORMATION Organization Part Number MU9C4K64-50TDC 4096 x 64 MU9C4K64-70TDC 4096 x 64 MU9C4K64-90TDC 4096 x 64 MU9C4K64-50TEC * 4096 x 64 MU9C4K64-70TDI 4096 x 64 MU9C4K64-90TDI 4096 x 64 MU9C8K64-35TDC 8192 x 64 MU9C8K64-50TDC 8192 x 64 MU9C8K64-70TDC 8192 x 64 MU9C8K64-90TDC 8192 x 64 MU9C8K64-35TEC * 8192 x 64 MU9C8K64-50TEC * 8192 x 64 ...