MU9C2480A-90DC Music Semiconductors, Inc., MU9C2480A-90DC Datasheet

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LANCAM A/L series APPLICATION BENEFITS The 256x64 to 4Kx64 LANCAM A/L series facilitate numerous operations: • Fast speed allows processing of both DA and SA within 450 ns, equivalent to 138 ports of 10 Base ports of 100 ...

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LANCAM A/L series (not recommended for new designs) GENERAL DESCRIPTION The LANCAM A/L series consists of various depths of 64-bit Content Addressable Memories (CAMs), with a 16-bit wide interface. CAMs, also known as associative memories, operate in the converse way ...

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Pin Descriptions PIN DESCRIPTIONS Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs should never be left floating. The CAM architecture draws large currents during compare ...

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LANCAM A/L series (not recommended for new designs) /MI (Match Input, Input, TTL) The /MI input prioritizes devices in vertically cascaded systems connected to the /MF output of the previous device in the daisy chain. The /MI pin ...

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Functional Description FUNCTIONAL DESCRIPTION The LANCAM is a Content Addressable Memory (CAM) with 16-bit I/O for network address filtering and translation, virtual memory, data compression, caching, and table lookup applications. The memory consists of static CAM, organized in 64-bit data ...

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LANCAM A/L series (not recommended for new designs) care” for the purpose of the comparison with all the memory locations. During a Data Write cycle or a MOV instruction, data in the specified active Mask register can also determine which ...

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Functional Description DQ15– /CM /EC Rev. 1 LANCAM A/L series (not recommended for new designs) 16 DQ15–0 /MI /E /FI /W LANCAM /FF /CM /EC /MF DQ15–0 /MI /E /FI /W LANCAM /FF /CM /EC /MF DQ15–0 /MI ...

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LANCAM A/L series (not recommended for new designs) OPERATIONAL CHARACTERISTICS Note: Throughout the following, “aaaH” represents a three-digit hexadecimal number “aaa,” while “bbB” represents a two-digit binary number “bb.” All memory locations are written to or read from in 16-bit ...

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Operational Characteristics removing the device from the daisy chain. With the Match Flag disabled, /MF=/MI and operations directed to Highest-Priority Match locations are ignored. Normal operation of the device is with the /MF enabled. The Match Flag Enable field has ...

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LANCAM A/L series (not recommended for new designs) Table 2: Input/Output Operations Cycle Type / I/O Status M W Cmd Write Cmd Read OUT OUT ...

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Operational Characteristics Table 3: Device Control State After Reset CAM Status Validity bits at all memory locations Match and Full Flag outputs IEEE 802.3–802.5 Input Translation CAM/RAM Partitioning Comparison Masking Address register auto-increment or auto-decrement Source and Destination Segment counters ...

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LANCAM A/L series (not recommended for new designs) Table 4: Standard and Enhanced Mode Device Select Response Case Internal Internal /EC(int) /MA(int ...

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Operational Characteristics set in the Control register. During shift rights, bits shifted off the LSB of the CAM partition reappear at the MSB of the CAM partition. Likewise, bits shifted off the MSB of the CAM partition reappear at the ...

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LANCAM A/L series (not recommended for new designs /CM /EC DQ15–0 /E /CM /W DQ15–0 /EC /MF /MA, /MM I/O Cycles The LANCAM supports four basic I/O cycles: Data Read, Data Write, Command Read, and Command Write. The ...

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Operational Characteristics Compare Operations During a Compare operation, the data in the Comparand register is compared to all locations in the Memory array simultaneously. Any Mask register used during compares must be selected beforehand in the Control register. There are ...

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LANCAM A/L series (not recommended for new designs) 15. When /EC is first taken LOW in a string of LANCAM devices (and assuming the Device Select registers are set to FFFFH), all devices respond to that command write or data ...

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Operational Characteristics initialization, all devices are empty, thus the top device in the string responds to a TCO PA instruction, and loads its PA register. A Set Full Flag (SFF) instruction advances to the next device in the string and ...

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LANCAM A/L series (not recommended for new designs) INSTRUCTION SET DESCRIPTIONS Notes: Instruction cycle lengths given in Table 6 on page 22. If f=1, the instruction requires an absolute address to be supplied on the following cycle as a Command ...

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Instruction Set Descriptions Instruction: Validity Bit Control (VBC) Binary Op-Code: 0000 f100 00dd dvvv f Address Field flag ddd Destination of data vvv Validity setting for Memory location The VBC instruction sets the Validity bits at the selected memory locations ...

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LANCAM A/L series (not recommended for new designs) INSTRUCTION SET SUMMARY Mnemonic Format: INS dst, src[msk], val INS: Instruction mnemonic dst: Destination of the data src: Source of the data msk: Mask register used val: Validity condition set at the ...

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Instruction Set Summary Instruction: Data Move (continued) Operation Mnemonic Mask Register 2 from: Comparand Register MOV MR2,CR Mask Register 1 MOV MR2,MR1 No Operation NOP Memory at Address Reg. MOV MR2,[AR] Memory at Address MOV MR2,aaaH Mem. at Highest-Prio. Match ...

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LANCAM A/L series (not recommended for new designs) Instruction Cycle Lengths Table 6: Instruction Cycle Lengths Cycle Length Command Write MOV reg, reg (except -70) TCO reg (except CT) TCO CT (non-reset, HMA invalid) Short SPS, SPD, SFR SBR, RSC ...

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Register Bit Assignments REGISTER BIT ASSIGNMENTS Control Register Bits Device Bit(s) Name 15 RST 14:13 Match Flag 12:11 Full Flag 10:9 Translation 8:6 CAM/RAM Part All 5:4 Comp. Mask 3:2 AR Inc/Dec 1:0 Mode Note: D15 reads back as 0. ...

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LANCAM A/L series (not recommended for new designs) Next Free Address Bits Device Bit(s) Name 15:8 PA7–0 3480A/L 7:0 NF7-0 15:9 PA6-0 5480A/L 8:0 NF8-0 15:10 PA5–0 1480A/L 9:0 NF9-0 15:11 PA4-0 2480A/L 10:0 NF10-0 15:12 PA3–0 4480A/L 11:0 NF11-0 ...

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Register Bit Assignments Persistent Source Register Bits Device Bit(s) Name 3480A/L 15:4 DEVID 5480A/L 15:4 DEVID 1480A/L 15:4 DEVID 2480A/L 15:4 DEVID 4480A/L 15:4 DEVID All 3:0 PS Note: The Persistent Source register is read only, and is accessed by ...

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LANCAM A/L series (not recommended for new designs) ELECTRICAL Absolute Maximum Ratings Supply Voltage: "A" -0.5 to 7.0 Volts "L" -0.5 to 4.6 Volts Voltage on all other pins -0.5 to VCC +0.5 Volts (-2 Volts for 10 ns, measured ...

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Switching Symbol Parameter I OZ Output leakage current Capacitance Symbol Parameter C IN Input capacitance C OUT Output capacitance AC Test Conditions Table 7: AC Test Conditions Input Signal Transitions 0.0 Volts to 3.0 Volts Input Signal Rise Time < ...

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LANCAM A/L series (not recommended for new designs) Switching Characteristics Table 9: Switching Characteristics No. Symbol Parameter 1 t ELEL Chip Enable Compare Cycle Time t ELEH 2 Chip Enable LOW Pulse Width 3 t EHEL Chip Enable HIGH Pulse ...

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Timing Diagrams TIMING DIAGRAMS Figure 12: Read Cycle /E /W /CM /EC /MI /MF /MA, /MM ...

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LANCAM A/L series (not recommended for new designs) PLCC PACKAGE 44-Pin PLCC Table 10: 44-Pin PLCC Dimensions Dim. A Dim. B 0.170 0.017 44-PIN PLCC 0.180 TYP Figure 15: 44-Pin PLCCPackage Dim. C Dim. D Dim. E Dim. E1 0.018 ...

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... Ordering Information ORDERING INFORMATION Part Number Cycle Time MU9C4480A-70DC MU9C4480A-90DC MU9C4480A-70DI MU9C4480A-90DI MU9C2480A-50DC MU9C2480A-70DC MU9C2480A-90DC MU9C2480A-70DI MU9C2480A-90DI MU9C1480A-50DC MU9C1480A-70DC MU9C1480A-90DC MU9C1480A-70DI MU9C1480A-90DI MU9C5480A-70DC MU9C5480A-90DC MU9C5480A-70DI MU9C5480A-90DI MU9C3480A-70DC MU9C3480A-90DC MU9C3480A-70DI MU9C3480A-90DI MU9C4480L-70DC MU9C4480L-90DC MU9C4480L-70DI MU9C4480L-90DI MU9C2480L-70DC MU9C2480L-90DC MU9C2480L-70DI MU9C2480L-90DI MU9C1480L-90DC MU9C1480L-90DI MU9C5480L-70DC ...

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LANCAM A/L series (not recommended for new designs) MUSIC Semiconductors’ agent or distributor: Worldwide Headquarters North American Sales MUSIC Semiconductors MUSIC Semiconductors 5850 T.G. Lee Blvd, Suite 345 121 Union Ave. , Suite 1 Orlando, FL 32822 Middlesex, NJ 08846 ...