m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 23

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m5m4v4s40ctp-12

Manufacturer Part Number
m5m4v4s40ctp-12
Description
2-bank 131072-word 16-bit Synchronous Dram
Manufacturer
Mitsumi Electronics, Corp.
Datasheet

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SDRAM (Rev. 0.3)
AUTO REFRESH
address is generated internally. 1024 REFA cycles issued within 16.4ms will refresh the entire 4Mbit
memory array. The auto-refresh is alternately performed on each bank (ping-pong). Before performing an
auto-refresh, both banks must be in the idle state. Subsequent commands (except NOP or DESELECT)
must not be asserted before tRC from the REFA command.
Feb ‘97 Preliminary
Auto-refresh is initiated with a REFA command (/CS= /RAS= /CAS= L, /WE= /CKE= H). The refresh
A0-8
/RAS
/CAS
CKE
CLK
/CS
/WE
BA
Auto Refresh on Bank 0
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
Auto-Refresh
MITSUBISHI ELECTRIC
M5M4V4S40CTP-12, -15
NOP or DESLECT
minimum tRC
Auto Refresh on Bank 1
MITSUBISHI LSIs
23

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