m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 13

• Manufacturer Part Number: m5m4v4s40ctp-12
• Description: 2-bank 131072-word 16-bit Synchronous Dram
• Manufacturer: Mitsumi Electronics, Corp.

[ CAS LATENCY ]
CLK determines which CL should be used. The DRAM column access, tCAC, determines the CL timing
requirements.
[ BURST LENGTH ]
performed after the initial write or read command. For BL=1,2,4,8 the output data is tristated (Hi-Z) after
the last read. For BL=FP (Full Page) the TBST (Burst Terminate) command must be used to stop the output
of data.
Command
SDRAM (Rev. 0.3)
Feb ‘97 Preliminary
/CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the speed of
The burst length, BL, determines the number of consecutive writes or reads that will be automatically
Address
Command
CLK
DQ
DQ
DQ
DQ
DQ
Address
CLK
DQ
DQ
DQ
ACT
X
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
tRCD
ACT
X
READ
Y
tRCD
Q0
Q0
Q0
Q0
Q0
READ
/CAS Latency Timing (BL=4)
Q1
Q1
Q1
Q1
MITSUBISHI ELECTRIC
Y
Burst Length Timing (CL=2)
Q2
Q2
Q2
M5M4V4S40CTP-12, -15
Q0
Full Page counter rolls over and continues to count.
Q3
Q3
Q3
Q0
Q1
Q4
Q4
Q1
Q0
Q2
Q5
Q5
Q2
Q1
Q3
Q6
Q6
Q3
Q2
Q7
Q7
Q8
Q3
Q255
MITSUBISHI LSIs
Q0
CL=1
CL=2
CL=3
Q1
BL=1
BL=2
BL=4
BL=8
BL=FP
13