IDT72V36102 IDT [Integrated Device Technology], IDT72V36102 Datasheet - Page 14

• Manufacturer Part Number: IDT72V36102
• Description: 3.3 VOLT CMOS SyncBiFIFO-TM
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
2. If FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where FWFT is LOW.
NOTES:
1. t
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
EFB/ORB
FS1,FS0
A0 - A35
FFB/IRB
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
FFA/IRA
FS1,FS0
FFA/IRA
edge of CLKB is less than t
SKEW1
FWFT
CLKA
CLKB
CLKB
RST1,
RST2
CLKA
MBF1
RST1
ENA
AEB
AFA
is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight
4
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
0,0
t
RSTS
t
SKEW1
FSS
t
FSH
, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
t
t
t
PRF
PRF
PRF
1
2
t
PIR
t
PIR
AFA Offset
(IDT Standard and FWFT Modes)
t
DS
(Y1)
TM
t
DH
t
ENS2
14
AEB Offset
(X1)
t
FSS
t
t
POR
ENH
AFB Offset
(Y2)
0,1
t
(1)
RSTH
(IDT Standard and FWFT Modes)
t
FSH
AEA Offset
COMMERCIAL TEMPERATURE RANGE
(X2)
t
FWS
1
t
SKEW1
First Word to FIFO1
(1)
t
2
PIR
t
PIR
4679 drw 06
4679 drw 05