IDT72V36102 IDT [Integrated Device Technology], IDT72V36102 Datasheet - Page 8

• Manufacturer Part Number: IDT72V36102
• Description: 3.3 VOLT CMOS SyncBiFIFO-TM
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Vcc = 3.3V
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
S
DS
DH
CLK
CLKH
CLKL
ENS1
ENS2
RSTS
FSS
FWS
ENH
RSTH
FSH
SKEW1
SKEW2
Symbol
(2)
(2,3)
±
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
Setup Time, A0-A35 before CLKA↑ and B0-B35
before CLKB↑
Setup Time, CSA and W/RA, before
CLKA↑; CSB, and W/RB before CLKB↑
Setup Time, ENA and MBA, before
CLKA↑; ENB, and MBB before CLKB↑
Setup Time, RST1 or RST2 LOW before CLKA↑
or CLKB↑
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
Setup Time, FWFT before CLKA↑
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/RB, ENB, and MBB after CLKB↑
Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
Skew Time, between CLKA↑ and CLKB↑ for EFA/ORA,
EFB/ORB, FFA/IRA, and FFB/IRB
Skew Time, between CLKA↑ and CLKB↑ for AEA,
AEB, AFA, and AFB
0.15V
;
T
A
(1)
= 0
ο
C to +70
Parameter
ο
C; JEDEC JESD8-A compliant)
TM
(1)
8
4.5
4.5
7.5
0.5
0.5
7.5
IDT72V36102L10
Min.
10
12
—
IDT72V3682L10
IDT72V3692L10
3
4
3
5
0
4
2
100
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COMMERCIAL TEMPERATURE RANGE
Min.
IDT72V36102L15
4.5
4.5
7.5
7.5
—
15
12
IDT72V3682L15
IDT72V3692L15
6
6
4
5
0
1
1
4
2
Max.
66.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns