IDT72V205 IDT [Integrated Device Technology], IDT72V205 Datasheet - Page 15

• Manufacturer Part Number: IDT72V205
• Description: 3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
NOTES:
1. D = maximum FIFO Depth.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset.
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
WCLK
RCLK
WCLK
WEN
RCLK
In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245.
In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245.
In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245.
In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245.
REN
PAF
WEN
REN
HF
Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
D - (m + 1) words in FIFO
[
D-1
2
Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes)
t
CLKH
D/2 words in FIFO
+ 1
]
words in FIFO
t
CLKH
(2)
,
(3)
t
ENS
t
ENS
(1)
t
CLKL
t
15
CLKL
TM
t
t
t
PAFA
ENH
ENH
t
HF
t
ENS
t
ENS
[
D-1
D/2 + 1 words in FIFO
2
D - m words
+ 2
in FIFO
]
words in FIFO
t
PAFA
t
HF
(2)
COMMERCIAL AND INDUSTRIAL
,
(3)
TEMPERATURE RANGES
[
D-1
D - (m + 1) words
2
D/2 words in FIFO
+ 1
in FIFO
]
words in FIFO
4294 drw 15
4294 drw 14
(2)
,
(3)