IDT72V205 IDT [Integrated Device Technology], IDT72V205 Datasheet - Page 14

• Manufacturer Part Number: IDT72V205
• Description: 3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
D
Q
WCLK
RCLK
WEN
WCLK
0
0
REN
RCLK
PAE
WEN
- D
REN
- Q
LD
LD
15
15
t
CLKH
Figure 13. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKH
PAE OFFSET
t
CLK
Figure 11. Write Programmable Registers (IDT Standard and FWFT Modes)
t
CLK
t
t
ENS
ENS
t
t
t
DS
ENS
ENS
t
n + 1 words in FIFO
CLKL
t
CLKH
Figure 12. Read Programmable Registers (IDT Standard Mode)
n words in FIFO
t
UNKNOWN
CLKL
PAF OFFSET
t
t
ENH
t
DH
ENH
(2) ,
t
(3)
A
t
ENS
t
CLKL
14
PAE OFFSET
TM
t
ENH
t
PAEA
t
ENS
n + 1 words in FIFO
n + 2 words in FIFO
D
0
- D
PAF OFFSET
11
PAE OFFSET
t
PAEA
(2) ,
(3)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
n + 1 words in FIFO
n words in FIFO
PAE OFFSET
4294 drw 12
4294 drw 13
4294 drw 11
(2) ,
(3)