RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 42

• Manufacturer Part Number: RM7000-300S
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
Table 20
Table 21
Table 22
Int*(9:0)
NMI*
JTDI
JTCK
JTDO
JTMS
BigEndian
VccOK
ColdReset*
Reset*
ModeClock
ModeIn
Pin Name
Pin Name
Pin Name
Interrupt Interface Pins
JTAG Interface Pins
Initialization Interface Pins
Type
Input
Input
Type
Input
Input
Output
Input
Type
Input
Input
Input
Input
Output
Input
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Description
Interrupt
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the
interrupt register.
Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit 6
in R5000 compatibility mode).
Description
JTAG data in
JTAG serial data in.
JTAG clock input
JTAG serial clock input.
JTAG data out
JTAG serial data out.
JTAG command
JTAG command signal, signals that the incoming serial data is
command data.
Description
Big Endian / Little Endian Control
Allows the system to change the processor addressing mode without
rewriting the mode ROM.
Vcc is OK
When asserted, this signal indicates to the RM7000 that the 2.5V
power supply has been above 2.25V for more than 100 milliseconds
and will remain stable. The assertion of VccOK initiates the reading of
the boot-time mode control serial stream.
Cold Reset
This signal must be asserted for a power on reset or a cold reset.
ColdReset must be de-asserted synchronously with SysClock.
Reset
This signal must be asserted for any reset sequence. It may be
asserted synchronously or asynchronously for a cold reset, or
synchronously to initiate a warm reset. Reset must be de-asserted
synchronously with SysClock.
Boot Mode Clock
Serial boot-mode data clock output at the system clock frequency
divided by two hundred and fifty six.
Boot Mode Data In
Serial boot-mode data input.
Non-maskable interrupt
Released
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