RM7000-266T PMC-Sierra Inc, RM7000-266T Datasheet
RM7000-266T
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RM7000-266T Summary of contents
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... RM7000™ Microprocessor with On-Chip Secondary Cache Proprietary and Confidential Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet RM7000 Datasheet Issue 1, January 2001 Released ...
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... PMC-Sierra, Inc. has been advised of the possibility of such damage. Trademarks RM7000 and Fast Packet Cache are trademarks of PMC-Sierra, Inc. Contacting PMC-Sierra PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC ...
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... Revision History Issue No. Issue Date 1 January 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet ECN Number Originator Details of Change 3618 T. Chapman Applied PMC-Sierra template to existing MPD (QED) FrameMaker document ...
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... All bit and field names described in the text, such as Interrupt Mask, are in an italic- bold typeface. All instruction names, such as MFHI, are in san serif typeface. • Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released 4 ...
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... Cache Management .....................................................................................................26 4.24 Primary Write Buffer .....................................................................................................27 4.25 System Interface ..........................................................................................................27 4.26 System Address/Data Bus ...........................................................................................28 4.27 System Command Bus ................................................................................................28 4.28 Handshake Signals ......................................................................................................28 4.29 System Interface Operation .........................................................................................29 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released 5 ...
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... Boot-Time Interface Parameters ..................................................................................48 11 Timing Diagrams ...................................................................................................................49 11.1 Clock Timing ................................................................................................................49 12 Packaging Information ..........................................................................................................50 13 RM7000 Pinout .....................................................................................................................51 14 Ordering Information .............................................................................................................53 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released 6 ...
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... Figure 10 Processor Block Write ..............................................................................................31 Figure 11 Multiple Outstanding Reads ......................................................................................31 Figure 12 Clock Timing .............................................................................................................49 Figure 13 Input Timing ..............................................................................................................49 Figure 14 Output Timing ...........................................................................................................49 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000A™ Microprocessor with On-Chip Secondary Cache Datasheet Released 7 ...
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... Table 18 Clock/control interface Pins ........................................................................................40 Table 19 Tertiary cache interfacePins .......................................................................................41 Table 20 Interrupt Interface Pins ...............................................................................................42 Table 21 JTAG Interface Pins ....................................................................................................42 Table 22 Initialization Interface Pins ..........................................................................................42 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000A™ Microprocessor with On-Chip Secondary Cache Datasheet Released 8 ...
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... Fully static CMOS design with dynamic power down logic • RM5271 pin compatible, 304 pin TBGA package, 31x31 mm Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released 9 ...
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... Cvt, Div, Sqrt Multiplier Array Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Extenal Cache Controller On-chip 256K Byte Secondary Cache, 4-way Set Associative Secondary Tags ...
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... It has two high-performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit. To keep its multiple execution units running efficiently, the RM7000 integrates not only 16 KB 4-way set associative instruction and data caches but backs them up with an integrated 256 KB 4-way set associative secondary as well ...
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... Superscalar Dispatch The RM7000 has an efficient symmetric superscalar dispatch unit which allows it to issue up to two instructions per cycle. For purposes of instruction issue, the RM7000 defines four classes of instructions: integer, load/store, branches, and floating-point. There are two logical pipelines, the function pipeline and the memory pipeline ...
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... The symmetric superscalar capability of the RM7000, in combination with its low latency integer execution units and high-throughput fully pipelined floating-point execution unit, provides unparalleled price/performance in computational intensive embedded applications. 4.3 Pipeline The logical length of both the F and M pipelines is five stages with state committing in the register write pipe stage ...
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... Register File The RM7000 has thirty-two general purpose registers with register location 0 (r0) hard wired to a zero value. These registers are used for scalar integer operations and address calculation. In order to service the two integer execution units, the register file has four read ports and two write ports and is fully bypassed both within and between the two execution units to minimize operation latency in the pipeline ...
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... Hi and Lo registers. These values can then be transferred to the general purpose register file using the Move-from-Hi and Move-from- addition to the baseline MIPS IV integer multiply instructions, the RM7000 also implements the 3-operand multiply instruction, MUL. This instruction specifies that the multiply result go directly to the integer register file rather than the Lo register ...
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... RM7000 to eliminate the need for a separate DSP engine in many embedded applications. By pipelining the multiply-accumulate function and dynamically determining the size of the input operands, the RM7000 is able to maximize throughput while still using an area efficient implementation. 4.7 Floating-Point Coprocessor The RM7000 incorporates a high-performance fully pipelined floating-point coprocessor which includes a floating-point register file and autonomous execution units for multiply/add/convert and divide/square root ...
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... In the MIPS architecture, the system control coprocessor (and thus the kernel software) is implementation dependent. For memory management, the RM7000 CP0 is logically identical to that of the RM5200 Family and R5000. For interrupt exceptions and diagnostics, the RM7000 is a superset of the RM5200 Family and R5000 implementing additional features described later in the sections on Interrupts, the Test/Breakpoint facility, and the Performance Counter facility ...
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... To support the non-blocking caches and enhanced interrupt handling capabilities of the RM7000, both the data and control register spaces of CP0 are supported by the RM7000. In the data register space, that is the space accessed using the MFC0 and MTC0 instructions, the RM7000 supports the same registers as found in the RM5200, R4000 and R5000 families ...
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... This mechanism is available to system software to provide a secure environment for user processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In the user mode, the RM7000 provides a single, uniform virtual address space of 256 32- bit mode). When operating in the kernel mode, four distinct virtual address spaces, totalling 1024 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address ...
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... ITLB is completely transparent to the user. 4.15 Data TLB The RM7000 uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB. Each DTLB entry maps page. The DTLB improves performance by allowing data address translation to occur in parallel with instruction address translation. When a miss occurs on a data Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’ ...
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... A 32-byte (eight instruction) line size is used to maximize the communication efficiency between the instruction cache and the secondary cache, tertiary cache, or memory system. The RM7000 is the first MIPS RISC microprocessor to support cache locking on a per line basis. The contents of each line of the cache can be locked by setting a bit in the Tag. Locking the line prevents its contents from being overwritten by a subsequent cache miss ...
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... resident, the cache contents will be updated and main memory will also be written leaving the write-back bit of the cache line unchanged; no writes will Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released 22 ...
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... With multiple levels of cache necessary to specify a policy for dealing with cases where two cache lines at level n of the hierarchy would, if possible, be sharing an entry in level n+1 of the hierarchy. The policy followed by the RM7000 is motivated by the desire to get maximum cache utility and results in the RM7000 allowing entries in the primaries which do not necessarily have a corresponding entry in the secondary ...
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... Like the RM5270, RM5271 and R5000, the RM7000 has direct support for an external cache. In the case of the RM527x chips this is a secondary cache whereas for the RM7000 this cache becomes a level-3, or tertiary cache. The tertiary cache is direct mapped and block write-through with byte parity protection for data ...
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... Other capabilities of the tertiary interface include block write, tag invalidate, and tag probe. For details of these transactions as well as detailed timing waveforms for all the tertiary transactions, see the R5000 or RM7000 Bus Interface Specifications. The tertiary cache tag can easily be implemented with standard components such as the Motorola MCM69T618. ...
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... Cache Locking The RM7000 allows critical code or data fragments to be locked into the primary and secondary caches. The user has complete control over what locking is performed with cache line granularity. For instruction and data fragments in the primaries, locking is accomplished by setting either or ...
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... MB/sec with a 125 MHz SysClock. Figure 8 shows a typical embedded system using the RM7000. This example shows a system with a bank of DRAMs, an optional tertiary cache, and an interface ASIC which provides DRAM control as well as an I/O port. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’ ...
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... Handshake Signals There are ten handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are used by an external device to indicate to the RM7000 whether it can accept a new read or write Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ ...
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... RM5271 and R5000. Support for multiple outstanding reads can be enabled or disabled via a boot- time mode bit. The RM7000 can issue read and write requests to an external device, while an external device can issue null and write requests to the RM7000. For processor reads, the RM7000 asserts ValidOut* and simultaneously drives the address and read command on the SysAD and SysCmd buses ...
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... The external agent retakes control of the bus and begins returning data (out of order) for the second miss to the processor. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Data0 Data1 NData ...
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... PAck* TcMatch 4.30 Data Prefetch The RM7000 is the first PMC-Sierra design to support the MIPS IV integer data prefetch ( PREF ) and floating-point data prefetch ( PREFX ) instructions. These instructions are used by the compiler assembly language programmer when it is known or suspected that an upcoming data reference is going to miss in the cache. By appropriately placing a prefetch instruction, the memory latency can be hidden under the execution of other instructions ...
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... To increase both observability and controllability of the processor thereby easing hardware and software debugging, a pair of Test/Break-point, or Watch, registers, Watch1 and Watch2, have been added to the RM7000. Each Watch register can be separately enabled to watch for a load address, a store address instruction address. All address comparisons are done on physical addresses ...
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... Note that only one event type can be counted at a time and that counting can occur for user code, kernel code, or both. The event types and control bits are listed in Table 10. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet 61 60:36 35:2 ...
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... The performance counter interrupt will only occur when interrupts are enabled in the Status register, IE=1, and Interrupt Mask bit 13 (IM[13]) of the coprocessor 0 interrupt control register is not set. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released 34 ...
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... When a hang occurs the interrupt ultimately triggers thereby breaking free from the hang-up. 4.35 Interrupt Handling In order to provide better real time interrupt handling, the RM7000 provides an extended set of hardware interrupts each of which can be separately prioritized and separately vectored. In addition to the six external interrupt pins available on the R4000 and R5000 family processors, the RM7000 provides four more interrupt pins for a total of ten external interrupts ...
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... The priority level registers are located in the coprocessor 0 control register space. For further details about the control space see the section describing coprocessor 0. In addition to programmable priority levels, the RM7000 also permits the spacing between interrupt vectors to be programmed. For example, the minimum spacing between two adjacent vectors is 0x20 while the maximum is 0x200 ...
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... Standby Mode The RM7000 provides a means to reduce the amount of power consumed by the internal core when the CPU would not otherwise be performing any useful operations. This state is known as Standby Mode. Executing the WAIT instruction enables interrupts and enters Standby Mode. When the WAIT instruction completes the W pipe stage, if the SysAD bus is currently idle, the internal processor clocks will stop thereby freezing the pipeline ...
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... External Tertiary cache RAM type: 0: Dual-cycle deselect (DCD) 1: Single-cycle deselect (SCD) Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Mode bit Description 17..16 System configuration identifiers - software visible in processor Config[21..20] register 19..18 ...
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... Output SysAD(63:0) Input/Output Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Description External request Signals that the system interface is submitting an external request. Release interface Signals that the processor is releasing the system interface to slave ...
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... System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. System Command/Data Identifier Bus Parity For the RM7000, unused on input and zero on output. Description System clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock ...
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... Input/Output Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Description Tertiary Cache Block Clear Requests that all valid bits be cleared in the Tag RAMs. Many RAM’s may not support a block clear therefore the block clear capability is not required for the cache to operate ...
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... Allows the system to change the processor addressing mode without rewriting the mode ROM. Vcc is OK When asserted, this signal indicates to the RM7000 that the 2.5V power supply has been above 2.25V for more than 100 milliseconds and will remain stable. The assertion of VccOK initiates the reading of the boot-time mode control serial stream ...
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... Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet > VccIO ...
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... As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG test mode. Refer to the RM7000 Family Users Manual, Appendix E. 4. VccP must be connected to VccInt through a passive filter circuit. See RM7000 Family User’s Manual for recommended circuit. ...
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... OL V VccIO - 0. 2. -0. 2. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Conditions Maximum 0.2V |I OUT 0.4V |I OUT 0.8V VccIO + 0. VccIO IN Released |= 100 A ...
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... Worst case instruction mix with worst case supply voltage. 3. I/O supply power is application dependant, but typically <10% of VccInt. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet CPU Clock Speed 200 MHz 250 MHz ...
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... JTAG Clock t JTAGCKP Period Note: Operation of the RM7000 is only guaranteed with the Phase Lock Loop Enabled. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Min Max ...
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... DS Setup Mode Data Hold t DH Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet CPU Speed 200 MHz Min Max Min mode14.. (fastest) 1.0 5.0 mode14.. ...
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... System Interface Timing (SysAD, SysCmd, ValidIn*, ValidOut*, etc.) Figure 13 Input Timing SysClock Data Figure 14 Output Timing SysClock Data Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet t t High Low t t Fall Rise t t ...
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... Note: All dimensions in millimeters unless otherwise indicated. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet E1, N ...
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... K21 L1 SysAD[10] L2 L20 Vcclnt L21 M1 VsslO M2 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Function Pin Function VssIO A3 VssIO VsslO A7 Do Not Connect A8 SysADC[1] A11 Do Not Connect A12 ...
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... AC12 VsslO AC13 SysCmd[2]* AC16 VsslO AC17 TcTOE* AC20 INT[5]* AC21 VsslO Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Function Pin Function SysAD[52] M22 SysAD[21] Vcclnt ...
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... Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet -123 T I Recommended Conversions RM7000-200T RM7000-250T RM7000-250T RM7000-266T RM7000-300T Released Temperature Grade: (blank) = commercial I = Industrial Package Type TBGA S = SBGA Device Maximum Speed ...
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... Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002175, Issue 1 RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released 54 ...