at572d940hf-cl ATMEL Corporation, at572d940hf-cl Datasheet - Page 9

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at572d940hf-cl

Manufacturer Part Number
at572d940hf-cl
Description
Diopsis 940hf Arm926ej-s Plus Gflops
Manufacturer
ATMEL Corporation
Datasheet
Table 3-1.
7010AS–DSP–07/07
Module
ETH
ETH
ETH
ETH
ETH
ETH
ETH
ETH
MCI
MCI
MCI
M JTAG
M JTAG
M JTAG
M JTAG
M JTAG
OSC
OSC
OSC
OSC
OSC
PIO A
PIO B
PIO C
PLL
PLL
PMC
Name
E_TXD0 -
E_TXD1
E_TXEN
E_REFCK
E_CRSDV
E_RXD0 -
E_RXD1
E_FCE100
E_MDIO
E_MDCK
MCCK
MCCDA
MCDA0-
MCDA3
M_NTRST
M_TCK
M_TDI
M_TDO
M_TMS
XIN
XOUT
X32IN
X32OUT
X32EN
PIOA0 -
PIOA31
PIOB0 -
PIOB31
PIOC0 -
PIOC31
PLL_RCA
PLL_RCB
A_CK
AT572D940HF
Function
Ethernet RMII Transmit Data Bus
Ethernet RMII Transmit Enable
Ethernet RMII Reference Clock
Ethernet RMII Carrier Sense/Data
Valid
Ethernet RMII Receive Data Bus
Ethernet RMII Force 100 Mb/s
operation
Ethernet RMII PHY Management
Data
Ethernet RMII PHY Management
Clock
Multimedia Card Clock
Multimedia Card Command
Multimedia Card Data
mAgicV JTAG Test Reset
mAgicV JTAG Test Clock
mAgicV JTAG Test Data Input
mAgicV JTAG Test Data Output
mAgicV JTAG Test Mode Select
Main Oscillator Quartz
Main Oscillator Quartz
Slow Clock Oscillator Quartz
Slow Clock Oscillator Quartz
Slow Clock Oscillator Enable
Parallel Input/Output A
Parallel Input/Output B
Parallel Input/Output C
PLL A Filter
PLL B Filter
ARM Clock
Pin Description
(Continued)
Type
bi-03
bi-03
bi-03
bi-03
bi-03
bi-03
bi-03
bi-03
bi-03
bi-03
bi-03
in
in
in
out-03
in
in
out
in
out
in
bi-03
bi-03
bi-03
in
in
bi-03
AT572D940HF Preliminary
Active
Level
high
high
Notes
output through PIO line
output through PIO line
input through PIO line
input through PIO line
input through PIO line
output through PIO line
through PIO line
output through PIO line
through PIO line
through PIO line
through PIO line
no pull-up resistor
no pull-up resistor
no pull-up resistor
internal pull-up resistor (internal
oscillator enabled)
general purpose programmable I/Os or
peripheral I/Os; Pulled-up input at reset
general purpose programmable I/Os or
peripheral I/Os; Pulled-up input at reset
general purpose programmable I/Os or
peripheral I/Os; Pulled-up input at reset
to be left floating (test input)
output through PIO line
for test purpose
9

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