at572d940hf-cl ATMEL Corporation, at572d940hf-cl Datasheet - Page 2

• Manufacturer Part Number: at572d940hf-cl
• Description: Diopsis 940hf Arm926ej-s Plus Gflops
• Manufacturer: ATMEL Corporation

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Ethernet MAC 10/100
AHB bus Matrix
System Controller (SYSC)
Power Management Controller (PMC)
Advanced Interrupt Controller (AIC)
Three 32-bit Parallel Input/Output Controllers (PIO)
Twenty-three Peripheral Data Controller (PDC) Channels
Debug Unit (DBGU)
Four Synchronous Serial Controllers (SSC)
Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
Two Master/Slave Serial Peripheral Interface (SPI)
One Three-channel 16-bit Timer/Counters (TC)
Two Two-Wire Interfaces (TWI)
Two CAN Interfaces
– Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
– USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
– Two dedicated PDC channels
– Reduced Media Independent Interface (RMII) to Physical Layer
– Integrated DMA channel
– Seven Masters and Five Slaves Handled
– Boot Mode Select Option
– Remap Command
– Reset Controller
– Periodic Interval Timer, Watchdog and Real-Time Timer
– Very Slow Clock (32768Hz) Operating Mode
– Software Programmable Power Optimization Capabilities
– 3 to 20 MHz On-chip Oscillator and two PLLs
– Four Programmable External Clock Signals
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up resistor and Synchronous Output
– 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention
– Two dedicated PDC channels
– Two Independent Clock and Frame Sync Pair Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
– Two dedicated PDC channels for each SSC
– Individual Baud Rate Generator, IrDA
– Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support
– Two dedicated PDC channels for each USART
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Two dedicated PDC channels for each SPI
– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
– Master Mode Support, All Two-wire Atmel EEPROM’s Supported
– Fully compliant with CAN 2.0 Part A and 2.0 Part B
AT572D940HF Preliminary
®
Infrared Modulation/Demodulation
7010AS–DSP–07/07