w332m72v ETC-unknow, w332m72v Datasheet - Page 7

• Manufacturer Part Number: w332m72v
• Description: 32mx72 Synchronous Dram
• Manufacturer: ETC-unknow

NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 defi ne the op-code written to the Mode Register and A12 should be driven
3. A0-12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-9 provide column address; A10 HIGH enables the auto precharge feature
COMMANDS
The Truth Table provides a quick reference of available
com mands. This is followed by a written de scrip tion of each
com mand. Three additional Truth Tables appear following
the Op er a tion section; these tables provide current state/
next state information.
COMMAND INHIBIT
The COMMAND INHIBIT function pre vents new commands
from being executed by the SDRAM, regardless of whether
the CLK signal is enabled. The SDRAM is effectively
de se lect ed. Op er a tions already in progress are not
affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to an SDRAM which is selected (CS# is LOW).
This pre vents unwanted commands from being registered
dur ing idle or wait states. Op er a tions already in progress
are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-11 (A12
should be driven low). See Mode Reg is ter heading in the
Register Defi ni tion sec tion. The LOAD MODE REGISTER
August 2005
Rev. 2
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
Write Enable/Output Enable (8)
Write Inhibit/Output High-Z (8)
low.
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
White Electronic Designs
TRUTH TABLE - COMMANDS AND DQM OPERATION (NOTE 1)
CS#
H
L
L
L
L
L
L
L
L
–
–
7
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs
command can only be issued when all banks are idle, and
a sub se quent ex e cut able com mand cannot be issued until
t
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs se lects the bank, and the
address pro vid ed on inputs A0-12 selects the row. This row
remains active (or open) for ac cess es until a PRECHARGE
com mand is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-9
se lects the starting column location. The value on input
A10 de ter mines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ
burst; if AUTO PRECHARGE is not selected, the row will
remain open for subsequent ac cess es. Read data appears
on the I/Os sub ject to the logic level on the DQM inputs
MRD
RAS#
precharged and BA0, BA1 are “Don’t Care.”
LOW.
Care” except for CKE.
(two-clock delay).
X
H
H
H
L
L
L
L
–
–
H
is met.
White Electronic Designs Corporation • [phone] • www.wedc.com
CAS#
X
H
H
H
H
L
L
L
L
–
–
WE#
H
H
H
H
X
–
–
L
L
L
L
DQM
L/H
L/H
W332M72V-XSBX
X
X
X
X
X
X
X
H
L
8
8
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
–
–
High-Z
Active
Active
Valid
I/Os
X
X
X
X
X
X
X