w332m72v ETC-unknow, w332m72v Datasheet

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w332m72v

Manufacturer Part Number
w332m72v
Description
32mx72 Synchronous Dram
Manufacturer
ETC-unknow
Datasheet
32Mx72 Synchronous DRAM
FEATURES
BENEFITS
* This product is subject to change without notice.
August 2005
Rev. 2
High Frequency = 100, 125, 133MHz
Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm
3.3V ±0.3V power supply for core and I/Os
Fully Synchronous; all signals registered on pos i tive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8192 refresh cycles
Rang es
Organized as 32M x 72
Weight: W332M72V-XSBX - 2.0 grams typical
73% SPACE SAV INGS
Re duced part count
Re duced I/O count
• 23% I/O Re duc tion
Re duced trace lengths for low er par a sit ic
ca pac i tance
Suitable for hi-re li abil i ty ap pli ca tions
Lami nate in ter pos er for op ti mum TCE match
Commercial, Industrial and Military Temperature
Count
Area
I/O
22.3
White Electronic Designs
TSOP
11.9
54
5 x 265mm
5 x 54 pins = 270 pins
Discrete Approach
TSOP
11.9
54
2
TSOP
11.9
= 1325mm
54
TSOP
11.9
54
2
1
GENERAL DESCRIPTION
The 256MByte (2Gb) SDRAM is a high-speed CMOS,
dy nam ic ran dom-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally confi gured as a
quad-bank DRAM with a syn chro nous interface. Each of
the chip’s 134,217,728-bit banks is or ga nized as 8,192
rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; ac cess es start at a selected location and continue
for a pro grammed number of locations in a programmed
se quence. Ac cess es be gin with the registration of an
ACTIVE com mand, which is then fol lowed by a READ or
WRITE com mand. The address bits reg is tered coincident
with the AC TIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits reg is tered co in ci dent
with the READ or WRITE com mand are used to se lect the
starting col umn lo ca tion for the burst ac cess.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be en abled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 2Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is com pat i ble
with the 2n rule of prefetch architectures, but it also allows
the column ad dress to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging
one bank while ac cess ing one of the other three banks
will hide the precharge cycles and provide seam less, high-
speed, random-access op er a tion.
The 2Gb SDRAM is designed to operate at 3.3V. An auto
refresh mode is provided, along with a power-saving,
power-down mode.
TSOP
11.9
54
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
ACTUAL SIZE
White Electronic Designs
208 Balls
352mm
W332M72V-XSBX
22
W332M72V-XSBX
2
16
23%
73%
G
A
N
S
V
S
I

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w332m72v Summary of contents

Page 1

... Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 8192 refresh cycles Commercial, Industrial and Military Temperature Rang es Organized as 32M x 72 Weight: W332M72V-XSBX - 2.0 grams typical BENEFITS 73% SPACE SAV INGS Re duced part count Re duced I/O count • 23% I/O Re duc tion Re duced trace lengths for low er par a sit ic ...

Page 2

... WE1# DQML3 DQML1 CAS1# RAS3# RAS1# CKE1 CKE3 CCQ CCQ CCQ SS CCQ 2 W332M72V-XSBX CCQ RAS0# RAS2 CCQ CAS0# WE0# WE2 DQ39 DQ7 NC NC DQ36 DQ4 DQ38 DQ6 ...

Page 3

... DQMH 3 WE# RAS# CAS 0-1 CLK CLK 4 U4 CKE CKE CS# 4 DQML DQML DQMH DQMH 4 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W332M72V-XSBX RAS # 0 CAS # RAS # 1 CAS # RAS # ...

Page 4

... Mode Register will power unknown state, it should be loaded prior to applying any operational command. August 2005 Rev. 2 W332M72V-XSBX Register Defi nition MODE REGISTER The Mode Register is used to defi ne the specifi c mode tion of the SDRAM. This defi nition includes the ...

Page 5

... Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-9 select the unique column to be accessed, and Mode Register bit M3 is ignored. 5 W332M72V-XSBX TABLE 1 – BURST DEFINITION Order of Accesses Within a Burst Starting Column Address ...

Page 6

... When the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W332M72V-XSBX DON'T CARE UNDEFINED T4 OH TABLE 2 – CAS LATENCY ...

Page 7

... tions already in progress are not affected. LOAD MODE REGISTER The Mode Register is loaded via inputs A0-11 (A12 should be driven low). See Mode Reg is ter heading in the Register Defi ni tion sec tion. The LOAD MODE REGISTER August 2005 Rev. 2 W332M72V-XSBX CS# RAS# CAS# WE# DQM H X ...

Page 8

... READ or WRITE com mand. AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not August 2005 Rev. 2 W332M72V-XSBX is sue another command to the same bank until the precharge time ( completed. This is determined explicit RP PRECHARGE com mand was issued at the earliest possible time ...

Page 9

... CAPACITANCE (NOTE 2) Symbol CI1 CA CI2 CIO BGA THERMAL RESISTANCE Symbol Theta JA Theta JB Theta JC 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W332M72V-XSBX Unit V V °C °C °C Max Unit ...

Page 10

... CCQ A (All other pins not under test = 0V) CC ≤ V OUT CCQ = +3.3V ± 0.3V; -55°C ≤ T ≤ +125° CCQ A 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W332M72V-XSBX Symbol Min Max 3.6 CC CCQ 0 -0.3 0.8 IL ...

Page 11

... REF t 16 REF RFC RRD t 0.3 1.2 0 CLK + 7ns 1 CLK + 7ns XSR 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W332M72V-XSBX -125 -133 Max Min Max 6 5 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1 1.8 120,000 50 120,000 ...

Page 12

... WRITE is executed. 24. Precharge mode only. 25. JEDEC and PC100 specify three clocks. 26. Parameter guaranteed by design. before going OH 27. Self refresh available in commercial and industrial temperatures only. 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W332M72V-XSBX -100 -125 -133 ...

Page 13

... ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES August 2005 Rev. 2 Bottom View 1.0 (0.039)NOM 10.0 (0.394) NOM 16.15 (0.636) MAX 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W332M72V-XSBX ...

Page 14

... SB = 208 Plastic Ball Grid Array (PBGA), 16mm x 22mm DEVICE GRADE Mil i tary -55°C to +125° dus tri al -40°C to +85° Com mer cial 0°C to +70°C August 2005 Rev. 2 ORDERING INFORMATION W 3 32M XXX White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W332M72V-XSBX ...

Page 15

... Changes (Pg 10, 11, 12, 14, 15) 2.1 Change status to Final 2.2 Add 133MHz speed 2.3 Update Capacitance Table data 2.4 Update Thermal Resistance Table data August 2005 Rev. 2 W332M72V-XSBX Release Date May 2004 November 2004 August 2005 15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com ...

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