mt9vddf6472phy-335 Micron Semiconductor Products, mt9vddf6472phy-335 Datasheet - Page 16

• Manufacturer Part Number: mt9vddf6472phy-335
• Description: 256mb, 512mb X72, Ecc, Pll, Sr 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

Figure 4:
PDF: 09005aef81eef7d4/Source: 09005aef81eef0df
DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
Pull-Down Characteristics
15. The refresh period 64ms. This equates to an average refresh rate of 7.8251µs. However,
16. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
17. To maintain a valid level, the transitioning edge of the input must:
18. V
19. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
20. Normal Output Drive Curves:
160
140
120
100
80
60
40
20
C. After the AC target level is reached, continue to maintain at least the target DC
C. The full variation in driver pull-up current from minimum to maximum process,
D. The variation in driver pull-up current within nominal limits of voltage and tem-
an AUTO REFRESH command must be asserted at least once every 70.3µs; burst
refreshing or posting by the DRAM controller greater than eight refresh cycles is not
allowed.
during REFRESH command period (
standby).
A. Sustain a constant slew rate from the current AC level through to the target AC
B. Reach at least the target AC level.
2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and
not exceed either -300mV or 2.2V, whichever is more positive.
A. The full variation in driver pull-down current from minimum to maximum pro-
B. The variation in driver pull-down current within nominal limits of voltage and
E. The full variation in the ratio of the maximum to minimum pull-up and pull-
0
F. The full variation in the ratio of the nominal pull-up to pull-down current should
0.0
DD
level, V
level, V
cess, temperature and voltage will lie within the outer bounding lines of the V-I
curve of Figure 4 on page 16.
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 4 on page 16.
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 5 on page 17
perature is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 5 on page 17.
down current should be between 0.71 and 1.4, for device drain-to-source voltages
from 0.1V to 1.0V, and at the same voltage and temperature.
be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
must not vary more than 4 percent if CKE is not active while any bank is active.
0.5
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
IL
IL
(
(
AC
DC
) or V
) or V
1.0
IH
IH
(
V
V
(
AC
DC
OUT
OUT
).
(V)
(V)
16
).
1.5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC [MIN]) else CKE is LOW (i.e., during
2.0
Minimum
2.5
©2005 Micron Technology, Inc. All rights reserved.
Notes