mt9vddf6472phy-335 Micron Semiconductor Products, mt9vddf6472phy-335 Datasheet
mt9vddf6472phy-335
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mt9vddf6472phy-335 Summary of contents
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... MT9VDDF6472PH(I) – 512MB For component specifications, refer to Micron’s Web site: Features • 200-pin, small-outline, dual in-line memory module (SODIMM) • Supports ECC error detection and correction • Fast data transfer rates: PC2100 and PC2700 • Utilizes 266 MT/s and 333 MT/s DDR SDRAM components • ...
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... MT9VDDF3272PHG-335_ MT9VDDF3272PHY-335_ MT9VDDF3272PHG-262_ MT9VDDF3272PHY-262_ MT9VDDF3272PHG-26A_ MT9VDDF3272PHY-26A_ MT9VDDF3272PH(I)G-265_ MT9VDDF3272PH(I)Y-265_ MT9VDDF6472PHG-335_ MT9VDDF6472PHY-335_ MT9VDDF6472PHG-262_ MT9VDDF6472PHY-262_ MT9VDDF6472PHG-26A_ MT9VDDF6472PHY-26A_ MT9VDDF6472PH(I)G-265_ MT9VDDF6472PH(I)Y-265_ Note: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDF3272PHG-265A1. ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... List of Figures Figure 1: 200-Pin SODIMM (MO-224 Figure 2: Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 3: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 4: Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 5: Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 6: Component Case Temperature vs. Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 7: Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 8: Definition of Start and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 9: Acknowledge Response from Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 10: SPD EEPROM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 11: 200-Pin SODIMM Dimensions ...
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... DD Table 9: I Specifications and Conditions – 512MB .13 DD Table 10: Capacitance .14 Table 11: Module and Component Speed Grade Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 12: PLL Clock Driver Timing Requirements and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18 Table 13: EEPROM Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 14: EEPROM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 15: Serial Presence-Detect EEPROM DC Operating Conditions .23 Table 16: Serial Presence-Detect EEPROM AC Operating Conditions ...
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... CKE0 146 DQ45 196 98 NC 148 DM5 198 100 A11 150 V 200 SS No components this side of module. (all even pins) pin SS ©2005 Micron Technology, Inc. All rights reserved. Symbol DQ46 DQ47 DQ52 DQ53 V DD DM6 DQ54 ...
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Table 4: Pin Descriptions Refer to Pin Assignment Tables on page 6 for pin number and symbol correlation. Pin Numbers Symbol 118, 119, 120 WE#, CAS#, RAS# 35, 37 CK0, CK0# 96 CKE0, 121 117, 116 BA0, BA1 99, 100, ...
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... Input/ Data I/Os: Data bus. Output SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to ...
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... Functional Block Diagram All resistor values are 22Ω unless otherwise specified. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part numbering guide at Standard modules use the following DDR SDRAM devices: MT46V32M8FG (256MB); MT46V64M8FN (512MB). Lead-free modules use the following DDR SDRAM devices: MT46V32M8BG (256MB) ...
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... DDR SDRAM devices to minimize system clock loading. PLL Operation A phase-lock loop (PLL) on the module is used to redrive the differential clock signals CK and CK# to the DDR SDRAM devices to minimize system clock loading. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presence-detect (SPD) ...
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Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
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Table 8: I Specifications and Conditions – 256MB DD DDR SDRAM components only; Notes: 1–5, 8, 10, 12, 42; notes appear on pages 15–17; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 9: I Specifications and Conditions – 512MB DD DDR SDRAM components only; Notes: 1–5, 8, 10, 12, 42; notes appear on pages 15–17; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...
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... Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Electrical Characteristics and Recommended AC Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets, available at www.micron.com/products/ddrsdram. Module speed grades correlate with component speed grades as shown in the following table: Table 11: Module and Component Speed Grade Table PDF: 09005aef81eef7d4/Source: 09005aef81eef0df DDF9C32_64x72PH_2 ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: Output ...
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The refresh period 64ms. This equates to an average refresh rate of 7.8251µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles ...
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... remain stable. Although I 41. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 42. When an input signal is HIGH or LOW defined as a steady state logic HIGH or LOW. PDF: 09005aef81eef7d4/Source: 09005aef81eef0df DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN 256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM 0 ...
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... Notes: 1. The timing and switching specifications for the PLL listed above are critical for proper operation of DDR SDRAM modules. These are meant subset of the parameters for the specific device used on the module. Detailed information for this PLL is avail- able in JEDEC Standard JESD82. ...
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... The component case temperature measurements shown above were obtained experimen- tally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules. Case tem- peratures charted represent worst-case component locations on modules installed in the internal slots of the system ...
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Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7 on page ...
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Figure 8: Definition of Start and Stop SCL SDA Figure 9: Acknowledge Response from Receiver SCL from Master Data Output from Transmitter Data Output from Receiver PDF: 09005aef81eef7d4/Source: 09005aef81eef0df DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN 256MB, 512MB: (x72, ECC, PLL, ...
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Table 13: EEPROM Device Select Code Most significant bit (b7) is sent first Select Code Memory Area Select Code (two arrays) Protection Register Select Code Table 14: EEPROM Operating Modes Mode RW Bit Current Address Read 1 0 Random Address ...
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Table 15: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA OUT INPUT LEAKAGE CURRENT: ...
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... Fundamental Memory Type 3 Number of Row Addresses on Ass’y 4 Number of Column Addresses on Ass’y 5 Number of Physical Ranks on DIMM 6 Module Data Width 7 Module Data Width (Continued) 8 Module Voltage Interface Levels t 9 SDRAM Cycle Time, CK (CAS Latency = 2.5) (see note 2) 10 SDRAM Access from Clock, 2 ...
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... MICRON 01–12 1– set to 7ns (0x70) for optimum BIOS compatibility. Actual device t RAS used for -265 modules is calculated from RP, RCD, and RAP for -335 modules indicated as 18ns to align with industry 25 Serial Presence-Detect MT9VDDF3272PH MT9VDDF6472PH ...
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... ECC, PLL, SR) 200-Pin DDR SODIMM FRONT VIEW 2.667 (67.75) 2.656 (67.45 0.039 (0.99) 0.018 (0.46) TYP. TYP. 2.504 (63.60) TYP. BACK VIEW No components this side of module. 0.165 (4.20) TYP. PIN 200 1.867 (47.40) TYP. ® 26 Package Dimensions MAX or typical where noted. MIN U5 1.244 (31.60) 1.256 (31.90) U10 0.787 (20.00) TYP. U11 PIN 199 0 ...