hys64t512020eu-3s-a Qimonda, hys64t512020eu-3s-a Datasheet - Page 4

• Manufacturer Part Number: hys64t512020eu-3s-a
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Qimonda

1) This
2) Precharge-All command for an 8 bank device will equal to
1.2
The
module family are Unbuffered DIMM modules “UDIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 512M × 64 (4GB) and as
ECC modules
density, intended for mounting into 240-pin connector
sockets.
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400E–555–12–G0" where 6400E
Rev. 1.0, 2008-06
06112008-YHWK-B105
Product Type
PC2-6400 (5-5-5)
HYS64T512020EU-25F-A
HYS72T512020EU-25F-A
PC2-6400 (6-6-6)
HYS64T512020EU-2.5-A
HYS72T512020EU-2.5-A
PC2-5300 (5-5-5)
HYS64T512020EU-3S-A
HYS72T512020EU-3S-A
DIMM
Density
4GB
4GB
where
means Unbuffered DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency =5,
Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.2 and produced
on the Raw Card "G".
Qimonda
t
PREA
t
nRP
value is the minimum value at which this chip will be functional.
= RU{
1)
Module
Organization
512M × 64
512M × 72
in 512M × 72 (4GB) in organization and
t
RP
HYS[64/72]T512020EU–[25F/2.5/3S]–A
Description
/
t
CK(avg)
} and
Compliance Code
4GB 2R×8 PC2–6400U–555–12–E0
4GB 2R×8 PC2–6400E–555–12–G0
4GB 2R×8 PC2–6400U–666–12–E0
4GB 2R×8 PC2–6400E–666–12–G0
4GB 2R×8 PC2–5300U–555–12–E0
4GB 2R×8 PC2–5300E–555–12–G0
t
RP
is the value for a single bank precharge.
Memory
Ranks
2
2
2)
t
RP
ECC/
Non-ECC
Non-ECC
ECC
+ 1 ×
4
t
The memory array is designed with 2 Gbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
device using the 2-pin I
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
CK
or
t
nRP
# of SDRAMs # of row/bank/column
16
18
+ 1 × nCK, depending on the speed bin,
Description
2 Ranks, Non-ECC
2 Ranks, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
HYS[64/72]T512020EU–[25F/2.5/3S]–A
Unbuffered DDR2 SDRAM Modules
bits
15/3/10
15/3/10
2
C protocol. The first 128 bytes are
Ordering Information
SDRAM Technology
2Gbit (×8)
2Gbit (×8)
2Gbit (×8)
2Gbit (×8)
2Gbit (×8)
2Gbit (×8)
Internet Data Sheet
Address Format
TABLE 2
TABLE 3
Decoupling
Raw
Card
E
G
2
PROM