hys64t512020eu-3s-a Qimonda, hys64t512020eu-3s-a Datasheet - Page 12

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hys64t512020eu-3s-a

Manufacturer Part Number
hys64t512020eu-3s-a
Description
240-pin Unbuffered Ddr2 Sdram Modules
Manufacturer
Qimonda
Datasheet
Rev. 1.0, 2008-06
06112008-YHWK-B105
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Abbreviation
SSTL
LV-CMOS
CMOS
OD
Description
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tri-state,
and allows multiple devices to share as a wire-OR.
12
HYS[64/72]T512020EU–[25F/2.5/3S]–A
Unbuffered DDR2 SDRAM Modules
Abbreviations for Buffer Type
Abbreviations for Pin Type
Internet Data Sheet
TABLE 6
TABLE 7

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