hb28j128mm3 Renesas Electronics Corporation., hb28j128mm3 Datasheet - Page 48

• Manufacturer Part Number: hb28j128mm3
• Description: Multimediacard 32 Mbyte/64 Mbyte/128 Mbyte/256 Mbyte/512 Mbyte
• Manufacturer: Renesas Electronics Corporation.

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
Command Response Timings
All timing diagrams use the following schematics and abbreviations:
S: Start bit (= 0)
T: Transmitter bit (Host = 1, Card = 0)
P: One-cycle pull-up (= 1)
E: End bit (= 1)
Z: High impedance state (-> = 1)
D: Data bits
*: Repeater
CRC: Cyclic redundancy check bits (7 bits for command or response, 16 bits for block data)
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while the Z-bit is driven to (respectively kept) HIGH by the pull-up
resistors R
timing of these Renesas MultiMediaCards, the following values are defined:
Timing Values
Symbol
N
N
N
N
N
N
N
Notes: 1. Refer to Chapter “Electrical Characteristics” for more details about the access time.
Rev.0.02, Sep.15.2004, page 48 of 89
CR
ID
AC
RC
CC
WR
ST
2. Refer to Chapter “Read, Write and Erase Time-out Conditions”.
CMD
respectively R
Value [clock cycles]
Min
2
5
2*
8
8
2
2
1
DAT
. Actively driven P-bits are less sensitive to noise superposition. For the
Max
64
5
TAAC + NSAC*
2
2
Description
Number of cycles between command and
response
Number of cycles between card identification
or card operation conditions command and the
corresponding response
Number of cycles between a command and the
start of a related data block
Number of cycles between the last response
and a new command
Number of cycles between two commands, if
no response will be sent after the first
command (e.g. broadcast)
Number of cycles between a write command
and the start of a related data block
Number of cycles between stop command and
valid read / write data end