k4s643232e-te ETC-unknow, k4s643232e-te Datasheet - Page 9

• Manufacturer Part Number: k4s643232e-te
• Description: Sdram 512k 32bit Banks Synchronous Dram Lvttl 3.3v
• Manufacturer: ETC-unknow

K4S643232E-TE/N
Note :
AC CHARACTERISTICS
CLK cycle time
CLK to valid
output delay
Output data hold time
CLK high pulse width
CLK low
pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter
Parameter
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
(AC operating conditions unless otherwise noted)
t
t
t
t
t
t
RRD(min)
RCD(min)
RP(min)
RAS(min)
RAS(max)
RC
Symbol
(
min
Symbol
)
t
t
t
t
t
SAC
t
t
t
t
SHZ
SLZ
CC
OH
CH
SH
CL
SS
Min
-50
1.5
2.5
10
15
15
40
55
10
5
2
2
3
2
3
1
1
-
-
-
-
- 9 -
-50
1000
Max
4.5
4.5
6
6
-
-
-
-
-
-
-
-
-
Version
Min
2.5
2.5
1.5
2.5
10
6
2
3
3
1
1
100
-
-
-
-
-60
12
18
18
42
60
-60
1000
Max
5.5
5.5
6
6
-
-
-
-
-
-
-
-
-
1.75
Min
2.5
10
7
2
3
3
3
3
1
1
-
-
-
-
-70
14
20
20
49
70
-70
CMOS SDRAM
Rev. 1.4 (Dec. 2001)
1000
Max
5.5
5.5
6
6
-
-
-
-
-
-
-
-
-
Unit
Unit
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1, 2
1
2
3
3
3
3
2
-