k4s643232e-te ETC-unknow, k4s643232e-te Datasheet - Page 8

• Manufacturer Part Number: k4s643232e-te
• Description: Sdram 512k 32bit Banks Synchronous Dram Lvttl 3.3v
• Manufacturer: ETC-unknow

K4S643232E-TE/N
AC OPERATING TEST CONDITIONS
(AC operating conditions unless otherwise noted)
OPERATING AC PARAMETER
Note :
CAS Latency
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
Number of valid
output data
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Notes :
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
(Fig. 1) DC output load circuit
1. The V
Parameter
870
DD
Parameter
condition of K4S643232E-60 is 3.135V ~ 3.6V
CAS Latency=3
CAS Latency=2
3.3V
1200
30pF
t
t
Symbol
t
t
t
t
t
t
t
RAS(max)
t
t
RRD(min)
RCD(min)
t
RAS(min)
CCD(min)
MRS(min)
RDL(min)
CDL(min)
BDL(min)
RC
CC(min)
RP(min)
CL
(
min
)
V
V
OH
OL
(DC) = 0.4V, I
(DC) = 2.4V, I
(V
DD
11
3
5
3
3
8
= 3.3V
-50
OL
10
OH
2
2
2
5
7
0.3V, T
- 8 -
= 2mA
= -2mA
A
= -25
10
See Fig. 2
3
6
3
3
7
tr/tf = 1/1
2.4/0.4
Value
Version
o
1.4
1.4
C to +85
100
Output
-60
2
2
1
1
1
2
2
1
10
2
2
2
5
7
o
C)
(Fig. 2) AC output load circuit
10
3
7
3
3
7
Z0 = 50
-70
CMOS SDRAM
Rev. 1.4 (Dec. 2001)
10
2
2
2
5
7
Unit
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Vtt = 1.4V
Unit
ns
us
ea
50
ns
30pF
V
V
V
Note
1
1
1
1
1
2
2
2
3
4