k4s161622d Samsung Semiconductor, Inc., k4s161622d Datasheet - Page 36

• Manufacturer Part Number: k4s161622d
• Description: 512k X 16bit X 2 Banks Synchronous Dram
• Manufacturer: Samsung Semiconductor, Inc.

CLOCK
K4S161622D
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page
A
ADDR
10
DQM
CKE
RAS
CAS
/AP
WE
DQ
CS
BA
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
0
Row Active
(A-Bank)
RAa
RAa
1
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding
3. Burst stop is valid at every burst length.
memory cell. It is defined by AC parameter of t
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
2
3
(A-Bank)
Write
CAa
DAa0 DAa1 DAa2 DAa3 DAa4
4
5
6
7
8
Burst Stop
RDL.
tBDL
9
HIGH
10
(A-Bank)
Write
DAb0 DAb1 DAb2 DAb3 DAb4
CAb
11
12
13
14
15
DAb5
CMOS SDRAM
*Note 2
16
Precharge
(A-Bank)
tRDL
17
18
: Don't care
19