k4s161622d Samsung Semiconductor, Inc., k4s161622d Datasheet - Page 20

• Manufacturer Part Number: k4s161622d
• Description: 512k X 16bit X 2 Banks Synchronous Dram
• Manufacturer: Samsung Semiconductor, Inc.

K4S161622D
13. About Burst Length Control
12. About Burst Type Control
Random
Interrupt
Random
Special
MODE
MODE
MODE
MODE
MODE
MODE
Basic
Basic
(Interrupted by Precharge)
Random column Access
Sequential Counting
Interleave Counting
RAS Interrupt
CAS Interrupt
t
CCD
Burst Stop
Full Page
BRSW
= 1 CLK
1
2
4
8
At MRS A
BL=1, 2, 4, 8 and full page.At Full page wrap-around.
At MRS A
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
At MRS A
At auto precharge, t
At MRS A
At auto precharge, t
At MRS A
At MRS A
At MRS A
Wrap around mode(Infinite burst length)should be stopped by burst stop,
RAS interrupt or CAS interrupt.
At MRS A
Read burst=1,2,4,8,full page Write burst=1
At auto precharge of write, tRAS should not be violate
Using burst stop command, any burst length control is possible.
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
t
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
t
RDL
BDL
= 1 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
3
3
2,1,0
2,1,0
2,1,0
2,1,0
2,1,0
9
= "0". See the BURST SEQUENCE TABLE. (BL=4,8)
= "1". See the BURST SEQUENCE TABLE. (BL=4,8)
= "1".
= "000".
= "001".
= "010".
= "011".
= "111".
RAS
RAS
should not be violated.
should not be violated.
CMOS SDRAM