m36l0r7060t1 STMicroelectronics, m36l0r7060t1 Datasheet - Page 9

• Manufacturer Part Number: m36l0r7060t1
• Description: 128 Mbit Multiple Bank, Multilevel, Burst Flash Memory And 64 Mbit Burst Psram, 1.8 V Supply, Multichip Package
• Manufacturer: STMicroelectronics

M36L0R7060T1, M36L0R7060B1
2
2.1
2.2
2.3
2.4
Signal descriptions
See
connect-ed to this device.
Address inputs (A0-A22)
Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. The
other lines (A22) is an input for the Flash memory component only.
The Address inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine. The Flash memory is accessed through the Chip
Enable signal (
through the Chip Enable signal (E
Data input/output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
For the PSRAM component, the upper Byte Data inputs/outputs (DQ8-DQ15) carry the data
to or from the upper part of the selected address when Upper Byte Enable (UB
Low. The lower Byte Data inputs/outputs (DQ0-DQ7) carry the data to or from the lower part
of the selected address when Lower Byte Enable (LB
LB
Latch Enable (L)
The Latch Enable pin is common to the Flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the
respective memory components: M69KB096AM for the PSRAM and M58LR128HTB for the
Flash memory.
Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components.
For details of how the Clock signal behaves, please refer to the datasheets of the respective
memory components: M69KB096AM for the PSRAM and M58LR128HTB for the Flash
memory.
P
Figure 1: Logic diagram
are disabled, the Data inputs/outputs are high impedance.
E
F
) and through the Write Enable signal (W
and
Table 1: Signal
P
) and the Write Enable signal (W
names, for a brief overview of the signals
P
) is driven Low. When both UB
F
), while the PSRAM is accessed
P
).
Signal descriptions
P
) is driven
P
and
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