m36l0r7060t1 STMicroelectronics, m36l0r7060t1 Datasheet - Page 11

• Manufacturer Part Number: m36l0r7060t1
• Description: 128 Mbit Multiple Bank, Multilevel, Burst Flash Memory And 64 Mbit Burst Psram, 1.8 V Supply, Multichip Package
• Manufacturer: STMicroelectronics

M36L0R7060T1, M36L0R7060B1
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
PSRAM Chip Enable input (E
The Chip Enable input activates the PSRAM when driven Low (asserted). When de-
asserted (V
or Deep Power-down mode, according to the RCR settings.
PSRAM Write Enable (W
Write Enable, W
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
PSRAM Output Enable (G
When held Low, V
memory.
PSRAM Upper Byte Enable (UB
The Upper Byte En-able, UB
DQ15) to or from the upper part of the selected address during a Write or Read operation.
PSRAM Lower Byte Enable (LB
The Lower Byte Enable, LB
DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LB
bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as E
PSRAM Configuration Register Enable (CR
When this signal is driven High, V
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
V
V
power supply for all Flash memory operations (Read, Program and Erase).
V
V
power supply for all PSRAM operations.
DDF
CCP
DDF
CCP
provides the power supply to the internal core of the Flash memory. It is the main
provides the power supply to the internal core of the PSRAM device. It is the main
supply voltage
supply voltage
P
and UB
IH
), the device is disabled, and goes automatically in low-power Standby mode
P
, controls the Bus Write operation of the PSRAM. When asserted (V
IL
P
, the Output Enable, G
are disabled (High) during an operation, the device will disable the data
P
, gates the data on the Lower Byte Data inputs/outputs (DQ0-
P
, gates the data on the Upper Byte Data inputs/outputs (DQ8-
IH
, bus read or write operations access either the value of
P
)
P
P
)
remains Low.
P
, enables the Bus Read operations of the
P
)
P
P
)
)
P
)
Signal descriptions
IL
), the
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