at52bc3221a ATMEL Corporation, at52bc3221a Datasheet - Page 9

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at52bc3221a

Manufacturer Part Number
at52bc3221a
Description
32-mbit Flash 8-mbit Psram Stack Memory
Manufacturer
ATMEL Corporation
Datasheet

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Figure 1. Data Polling Algorithm
(Configuration Register = 00)
Notes:
3466A–STKD–11/04
NO
1. VA = Valid address for programming. During a sec-
2. I/O7 should be rechecked even if I/O5 = “1”
Successful, Write
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
because I/O7 may change simultaneously with
I/O5.
Read I/O7 - I/O0
Read I/O7 - I/O0
Program/Erase
I/O3, I/O5 = 1?
Exit Command
Operation Not
I/O7 = Data?
Product ID
I/O7 = Data?
Addr = VA
Addr = VA
START
NO
YES
NO
YES
YES
Program/Erase
Successful,
Read Mode
Operation
Device in
Figure 2. Data Polling Algorithm
(Configuration Register = 01)
Note:
NO
1. VA = Valid address for programming. During a sec-
Successful, Write
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Program/Erase
I/O3, I/O5 = 1?
Exit Command
Operation Not
Toggle Bit =
Toggle Bit =
Product ID
Toggle?
Toggle?
START
Twice
YES
YES
YES
NO
NO
Program/Erase
Successful
Operation
9

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