at52bc3221a ATMEL Corporation, at52bc3221a Datasheet - Page 30

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at52bc3221a

Manufacturer Part Number
at52bc3221a
Description
32-mbit Flash 8-mbit Psram Stack Memory
Manufacturer
ATMEL Corporation
Datasheet

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Read Cycle (1)
(Address Controlled, PCS1 = POE = V
Read Cycle (2)
(ZZ = PWE = V
Notes:
Page Read Cycle
(ZZ = PWE = V
Notes:
30
1. t
2. At any given temperature and voltage condition, t
3. Do not access device with cycle timing shorter than t
1. t
2. At any given temperature and voltage condition, t
3. Do not access device with cycle timing shorter than t
AT52BC3221A(T)
voltage levels.
device interconnection.
voltage levels.
device interconnection.
HZ
HZ
and t
and t
IH
IH
)
, 16 Words Access)
Address
Data Out
PUB, PLB
Address
Data Out
OHZ
OHZ
PUB, PLB
Data Out
A4~ A20
PCS1
A0~ A3
POE
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
PCS1
OE
High-Z
Previous Data Valid
High-Z
IL
t
t
BLZ
LZ
, ZZ = PWE = V
t
AA
t
t
CO
RC
t
BA
t
OE
t
OLZ
Data Valid
t
PAA
t
PC
Data Valid
Z
H
IH
t
HZ
HZ
PAA
A
, PUB or/and PLB = V
t
PC
RC
RC
(max) is less than t
(max) is less than t
LZ
A
Data Valid
A
E
(t
(t
t
WC
WC
PAA
t
t
MRC
PC
) for continuous periods > 40 µs.
) for continuous periods > 20 µs.
Data Valid
t
PAA
t
PC
Data Valid
t
PAA
Data Valid
LZ
t
LZ
PC
Data Valid
(min) both for a given device and from device to
(min) both for a given device and from device to
IL
)
t
PAA
t
PC
Data Valid
Data Valid
t
PAA
t
PC
Data Valid
H
HZ
t
OH
t
t
t
HZ
OHZ
BHZ
3466A–STKD–11/04

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