at52bc3221a ATMEL Corporation, at52bc3221a Datasheet
at52bc3221a
Available stocks
Related parts for at52bc3221a
at52bc3221a Summary of contents
Page 1
... ISB0 < 10 µA when Deep Power-Down Flash Boot Device Number Location AT52BC3221A Bottom AT52BC3221AT Top Flash Plane PSRAM Configuration Configuration 32M (2M x 16) 8M (512K x 16) 32M (2M x 16) 8M (512K x 16) 32-Mbit Flash + 8-Mbit PSRAM Stack Memory AT52BC3221A AT52BC3221AT Preliminary Rev. 3466A–STKD–11/04 1 ...
Page 2
... PLB PUB PVCC PGND PCS1 ZZ PWE POE CBGA (Top View) AT52BC3221A(T) 2 Function Common Address Input for 8M PSRAM/Flash, Flash Address Input Flash Chip Enable Flash Output Enable Flash Write Enable Flash Reset Flash READY/BUSY Output Flash Power Supply for Accelerated Program/Erase Operations ...
Page 3
... Block Diagram Description The AT52BC3221A(T) combines a 32-megabit Flash (2M x 16) and an 8-megabit PSRAM (organized as 512K x 16 stacked 66-ball CBGA package. The stacked modules operate at 2.7V to 3.3V in the extended temperature range. Absolute Maximum Ratings Temperature under Bias................................... -25°C to +85°C Storage Temperature ..................................... -55°C to +150°C ...
Page 4
... It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. Block Diagram AT52BC3221A( 0.9V or above, normal program and erase opera- PP ...
Page 5
Device READ: The 32-Mbit Flash memory is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are Operation asserted on the outputs. The ...
Page 6
... I/O5 status bit will be set high, indicating the program (erase) opera- tion did not complete as requested. Once the erase/program status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. The AT52BC3221A(T) 6 voltage is less that 0.4V. When ...
Page 7
Please see “Status Bit Table” on page 11 for more details. V STATUS BIT: The device provides a status bit on I/O3, which provides ...
Page 8
... INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from AT52BC3221A(T) 8 power-on delay: once less than V ...
Page 9
Figure 1. Data Polling Algorithm (Configuration Register = 00) START Read I/O7 - I/O0 Addr = VA YES I/O7 = Data I/O3, I/ YES Read I/O7 - I/O0 Addr = VA I/O7 = Data? NO Program/Erase ...
Page 10
... Program/Erase Operation Not Successful, Write Product ID Exit Command Note: 1. The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop toggling as I/O5 changes to “1”. AT52BC3221A(T) 10 Figure 4. Toggle Bit Algorithm (Configuration Register = 01) NO Program/Erase Operation Successful Note: 1 ...
Page 11
Status Bit Table I/O7 Configuration Register Programming I/O7 Erasing Erase Suspended & Read Erasing Sector Erase Suspended & Read DATA Non-erasing Sector Erase Suspended & I/O7 Program Non-erasing Sector Notes: 1. I/O5 switches to a “1” when a program or ...
Page 12
... Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User Note: All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A20 - AT52BC3221A(T) 12 (1) 2nd Bus 3rd Bus Cycle Cycle Data Addr Data Addr Data D OUT (2) AA ...
Page 13
Bottom Boot – Sector Address Table Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 ...
Page 14
... SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 AT52BC3221A(T) 14 x16 Address Range (A20 - A0) F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF ...
Page 15
Top Boot – Sector Address Table Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 ...
Page 16
... SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 AT52BC3221A(T) 16 x16 Address Range (A20 - A0) 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF ...
Page 17
DC and AC Operating Range Operating Temperature (Case) V Power Supply CC Operating Modes Mode CE OE Read V IL (2) Program/Erase V IL Standby/Program Inhibit Program Inhibit X X Output Disable X Reset X Product Identification ...
Page 18
... Input High Voltage IH V Output Low Voltage OL1 V Output Low Voltage OL2 V Output High Voltage OH1 V Output High Voltage OH2 Note the erase mode mA. CC AT52BC3221A(T) 18 Condition I 0. MHz OUT ...
Page 19
AC Read Characteristics Symbol Parameter t Read Cycle Time RC t Address to Output Delay ACC ( Output Delay CE ( Output Delay OE (3)( Output Float DF Output ...
Page 20
... Input Test Waveforms and Measurement Level Output Test Load Pin Capacitance ( MHz 25°C Symbol Typ OUT Note: This parameter is characterized and is not 100% tested. AT52BC3221A( < Max 6 12 Units Conditions OUT ...
Page 21
AC Word Load Characteristics Symbol Parameter Address, OE Setup Time AS OES t Address Hold Time AH t Chip Select Setup Time CS t Chip Select Hold Time CH t Write Pulse Width (WE or CE) WP ...
Page 22
... For chip erase, the address should be 555. For sector erase, the address depends on what sector erased. (See note 3 under “Command Definitions in Hex” on page 12.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. AT52BC3221A(T) 22 PROGRAM CYCLE ...
Page 23
Data Polling Characteristics Symbol Parameter t Data Hold Time Hold Time OEH ( Output Delay OE t Write Recovery Time WR Notes: 1. These parameters are characterized and not 100% tested. 2. See t ...
Page 24
... The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH(x16) Device Code: 00C8 (x16)-Bottom Boot 00C9H (x16)-Top Boot. 6. Either one of the Product ID Exit commands can be used. AT52BC3221A(T) 24 (1) Sector Lockdown Enable Algorithm (1)(6) LOAD DATA F0 TO ANY ADDRESS ...
Page 25
PSRAM The Pseudo-SRAM (PSRAM integrated memory based on a self-refresh DRAM array. The device is offered with density of 8-Mbit organized as 512,288 words by 16 bits Description designed to be identical in operation and interface ...
Page 26
... Overshoot and undershoot are sampled, not 100% tested. 3. Overshoot 1.0V in case of pulse width < Undershoot: -1.0V in case of pulse width < 20 ns. (1) Capacitance ( MHz, T Item Symbol Input Capacitance C IN I/O Capacitance C I/O Note: 1. Capacitance is sampled, not 100% tested. AT52BC3221A(T) 26 PLB PUB I/ I/ (1) ( High-Z High-Z (1) ( High-Z High-Z ...
Page 27
DC and Operating Characteristics Item Symbol Input Leakage Current I LI Output Leakage Current CC1 Average Operating Current I CC2 Output Low Voltage V OL Output High Voltage V OH Standby Current (TTL Standby Current ...
Page 28
... Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Page Mode Cycle Time Page Page Mode Address Access Time Maximum Cycle Time PCS1 High Pulse Width AT52BC3221A( 2.7V – 3.3V -25°C to 85° Symbol t t ...
Page 29
Power Up 1. Apply Power. Sequence 2. Maintain stable power for a minimum of 200 µs with PCS1 = V Standby Mode State Machines Standby Mode Characteristics Low Power Modes 3466A–STKD–11/04 Power On PCS1 = V Initial State Wait 200 ...
Page 30
... HZ OHZ voltage levels any given temperature and voltage condition, t device interconnection not access device with cycle timing shorter than t AT52BC3221A( PWE = V , PUB or/and PLB = ...
Page 31
Write Cycle (1) (PWE Controlled Address PCS1 PUB, PLB PWE Data In Data Out Write Cycle (2) (PCS1 Controlled Address PCS1 PUB, PLB PWE Dat a In Data Out Write ...
Page 32
... PCS1 going low to end of write measured from the address valid to the beginning of write measured from the end of write to the address change not access device with cycle timing shorter than t AT52BC3221A( MRC ...
Page 33
Deep Power-down Mode Entry/Exit A4 PCS1 PUB, PLB PWE ZWE ZZ Parameter t ZZWE t (Deep Power-down Mode Only ZZmin 3466A–STKD–11/04 C (4) R ( ZZmin Register Deep Power Write (DPD) Down Start Description ...
Page 34
... Ordering Information t (ns) Ordering Code ACC 70 AT52BC3221A-70CI 70 AT52BC3221AT-70CI 66C5 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA) AT52BC3221A(T) 34 Flash Boot Block Flash Plane Architecture Bottom 32M – Single Bank Top 32M – Single Bank Package Type PSRAM Package Operation Range 512K x 16 ...
Page 35
Packaging Information 66C5 – CBGA Marked A1 Identifier D 0.60 REF Øb 2325 Orchard Parkway San Jose, CA 95131 R 3466A–STKD–11/04 E Top View E1 A1 Ball Corner ...
Page 36
... Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2004. All rights reserved. Atmel are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...