at52bc1661a ATMEL Corporation, at52bc1661a Datasheet - Page 30

• Manufacturer Part Number: at52bc1661a
• Description: 16-mbit Flash + 8-mbit Psram Stack Memory
• Manufacturer: ATMEL Corporation

Write Cycle (1)
(PWE Controlled, ZZ = V
Write Cycle (2)
(PCS1 Controlled, ZZ = V
Write Cycle (3)
(PUB, PLB Controlled, ZZ = V
Notes:
30
1. A write occurs during the overlap (t
2. t
3. t
4. t
5. Do not access device with cycle timing shorter than t
AT52BC1661A(T) [Preliminary]
asserting PUB or PLB for single byte operation or simultaneously asserting PUB and PLB for double byte operation. A write
ends at the earliest transition when PCS1 goes high and PWE goes high. The t
the end of write.
CW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the PCS1 going low to end of write.
is measured from the end of write to the address change. t
PUB, PLB
PUB, PLB
PUB, PLB
Data Out
Data Out
Data Out
Address
Address
Address
Data In
Dat a In
Data In
PCS1
IH
PCS1
PCS1
PWE
PWE
PWE
IH
)
)
IH
)
Data Undefined
WP
) of low PCS1 and PWE. A write begins when PCS1 goes low and PWE goes low with
S
S
High-Z
High-Z
High-Z
S
RC
HZ
(t
WC
) for continuous periods > 40 µs.
W
W
(2)
(2)
W
C
C
C
W
W
W
WR
(2)
W
W
W
P
P
(1)
P
(1)
(1)
applied in case a write ends as PCS1 or PWE going high.
W
Data Valid
Data Valid
W
Data Valid
W
WP
R
(4)
is measured from the beginning of write to
W
R
R
(4)
(4)
High-Z
High-Z
High-Z
3455A–STKD–11/04