at52bc1661a ATMEL Corporation, at52bc1661a Datasheet - Page 13

• Manufacturer Part Number: at52bc1661a
• Description: 16-mbit Flash + 8-mbit Psram Stack Memory
• Manufacturer: ATMEL Corporation

Command Definition in Hex
Notes:
Flash Protection Register Addressing Table
Note:
3455A–STKD–11/04
Command
Sequence
Read
Chip Erase
Sector Erase
Word Program
Dual Word Program
Enter Single Pulse
Program Mode
Single Pulse Word
Program
Sector Lockdown
Erase/Program
Suspend
Erase/Program
Resume
Product ID Entry
Product ID Exit
Product ID Exit
Program Protection
Register
Lock Protection
Register - Block B
Status of Block B
Protection
Set Configuration
Register
CFI Query
Word
0
1
2
3
4
5
6
7
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS FORMAT shown
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 14 - 16 for details).
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled.
5. Either one of the Product ID Exit commands can be used.
6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
7. The default state (after power-up) of the configuration register is “00”.
8. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.
9. This fast programming option enables the user to program two words in parallel only when V
All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.
for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are don’t care.
the two words, D
(5)
(5)
(9)
Factory
Factory
Factory
Factory
User
User
User
User
Use
Cycles
Bus
1
6
6
4
5
6
1
6
1
1
3
3
1
4
4
4
4
1
IN1
and D
Addr
Addr
Addr
XXX
XXX
XXX
X55
555
555
555
555
555
555
555
555
555
555
555
555
1st Bus
IN2
Cycle
Block
, must only differ in address A0. This command should be used during manufacturing purposes only.
A
A
A
A
B
B
B
B
Data
D
F0
D
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B0
30
98
OUT
IN
(8)
(1)
AAA
AAA
Addr
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
2nd Bus
A7
(2)
(2)
Cycle
1
1
1
1
1
1
1
1
Data
55
55
55
55
55
55
55
55
55
55
55
55
A6
0
0
0
0
0
0
0
0
Addr
555
555
555
555
555
555
555
555
555
555
555
555
3rd Bus
Cycle
AT52BC1661A(T) [Preliminary]
A5
Data
F0
0
0
0
0
0
0
0
0
A0
E0
C0
C0
D0
80
80
80
80
90
90
(8)
Addr
Addr1
Addr
Addr
XXX
555
555
555
555
080
80
A4
0
0
0
0
0
0
0
0
4th Bus
Cycle
00/01
D
Data
D
OUT
D
D
AA
AA
AA
AA
X0
PP
IN1
IN
IN
A3
(6)
(7)
= 12V. The Addresses, Addr1 and Addr2, of
0
0
0
0
0
0
0
1
Addr
Addr2
AAA
AAA
AAA
AAA
5th Bus
Cycle
A2
0
0
0
1
1
1
1
0
Data
D
55
55
55
55
IN2
A1
0
1
1
0
0
1
1
0
SA
SA
Addr
555
555
(3)(4)
(3)(4)
6th Bus
Cycle
A0
1
0
1
0
1
0
1
0
Data
A0
10
30
60
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