at52bc1661a ATMEL Corporation, at52bc1661a Datasheet
at52bc1661a
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at52bc1661a Summary of contents
Page 1
... Access Time • Fully Static Operation and Tri-state Output • ISB0 < 10 µA when Deep Power-Down Device Number Flash Configuration AT52BC1661A(T) PSRAM Configuration 8M (512K x 16) 16M (1M x 16) 16-Mbit Flash + 8-Mbit PSRAM Stack Memory AT52BC1661A AT52BC1661AT Preliminary Rev. 3455A–STKD–11/04 1 ...
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... CBGA Top View Pin Pin Name Configurations A0 - A18, A19 CE OE/POE WE/PWE VCC VPP I/O0-I/O15 PCS1 RDY/BUSY PVCC GND/PGND PUB PLB NC RESET ZZ AT52BC1661A(T) [Preliminary A11 A15 A14 B A16 A8 A10 RDY BUSY D PGND RESET E NC VPP A19 ...
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... Description The AT52BC1661A(T) combines a single 16-Mbit Flash and a 8-Mbit PSRAM: both of the devices are offered in a stacked 66-ball CBGA package. The devices operate at 2.7V to 3.3V in the extended temperature range. Block Diagram Absolute Maximum Ratings Temperature under Bias................................... -25°C to +85°C Storage Temperature ..................................... -55°C to +150°C ...
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... Flash Memory Block Diagram OUTPUT BUFFER INPUT A0 - A19 BUFFER ADDRESS LATCH Y-DECODER X-DECODER AT52BC1661A(T) [Preliminary] 4 I/O0 - I/O15 INPUT BUFFER IDENTIFIER REGISTER STATUS REGISTER COMMAND REGISTER DATA COMPARATOR WRITE STATE MACHINE Y-GATING MAIN MEMORY RESET RDY/BUSY PROGRAM/ERASE VPP VOLTAGE SWITCH VCC GND 3455A– ...
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... When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not input is below 0.4V, the program and ...
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... Definition in Hex” table on page 13, the value of the configuration register can be changed. Voltages applied to the RESET pin will not alter the value of the configuration regis- ter. The value of the configuration register will affect the operation of the I/O7 status bit as described below. AT52BC1661A(T) [Preliminary] 6 voltage is less that 0.4V. When V SEC ...
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... This feature does not have to be activated; any sector’s usage as a write-protected region is optional to the user. 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] status bit has been set to a “1”, the system must write the PP status ...
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... To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the “Command Definition in Hex” table on page 13. To lock out block B, the four-bus cycle Lock Protection Register command AT52BC1661A(T) [Preliminary] 8 3455A–STKD–11/04 ...
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... INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] power-on delay: once less than V ...
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... During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5. AT52BC1661A(T) [Preliminary] 10 Figure 2. Data Polling Algorithm (Configuration Register = 01) YES Program/Erase Operation ...
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... Product ID Exit Command Note: 1. The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop toggling as I/O5 changes to “1”. 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] Figure 4. Toggle Bit Algorithm (Configuration Register = 01) Program/Erase Operation Successful, Device in Read Mode ...
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... Program Suspended & Read DATA Non-programming Sector Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. I/O3 switches to a “1” when the V AT52BC1661A(T) [Preliminary] 12 I/O7 I/O6 01 00/01 0 ...
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... Factory 4 User 5 User 6 User 7 User Note: All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] (1) 2nd Bus 3rd Bus Cycle Cycle Data Addr Data Addr Data D OUT ...
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... SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 AT52BC1661A(T) [Preliminary] 14 Size (Words 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K ...
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... SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K ...
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... Refer to AC programming waveforms on page 21 12.0V ± 0.5V Manufacturer Code: 001FH, Device Code: 00C0H – Bottom Boot, 00C2H, Top Boot. 5. See details under “Software Product Identification Entry/Exit” on page 23 (min) = 0.9V; V (max) = 3.6V. IHPP IHPP 7. V (max) = 0.4V. ILPP AT52BC1661A(T) [Preliminary] 16 Extended WE RESET (6) ...
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... IH V Output Low Voltage OL1 V Output Low Voltage OL2 V Output High Voltage OH1 V Output High Voltage OH2 Note the erase mode mA. CC 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] Condition Min I 0. MHz ...
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... OUTPUT Notes may be delayed may be delayed without impact ACC specified from OE or CE, whichever occurs first ( pF This parameter is characterized and is not 100% tested. AT52BC1661A(T) [Preliminary] 18 tRC ADDRESS VALID tCE tOE tACC tRO HIGH Z OUTPUT - t ...
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... Input Test Waveforms and Measurement Level Output Test Load Pin Capacitance ( MHz 25°C Symbol Typ OUT Note: This parameter is characterized and is not 100% tested. 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary < 2. 1029 Ohm (1) 1728 Ohm CL Max 6 12 Units ...
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... Chip Select Hold Time CH t Write Pulse Width ( Data Setup Time Data, OE Hold Time DH OEH t Write Pulse Width High WPH AC Word Load Waveforms WE Controlled CE Controlled AT52BC1661A(T) [Preliminary] 20 Min Max Units ...
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... For chip erase, the address should be 555. For sector erase, the address depends on what sector erased. (See note 3 under “Command Definitions in Hex” on page 13.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] PROGRAM CYCLE t t ...
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... Toggle Bit Waveforms Notes: 1. Toggling either both OE and CE will operate toggle bit. The t input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. AT52BC1661A(T) [Preliminary] 22 (1) tOEH tOE HIGH Z An ...
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... The device returns to standard operation mode. 5. Manufacturer Code: 001FH(x16) Device Code: 00C0H (x16) - Bottom Boot; 00C2H (x16) - Top Boot. 6. Either one of the Product ID Exit commands can be used. 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] (1) Sector Lockdown Enable Algorithm (1)(6) LOAD DATA F0 TO ANY ADDRESS ...
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... Very Low Standby Current – I • Very Low Operating Current – 1 3.0 and 1 µs (Typical) • Memory Expansion with PCS1 and POE • TTL Compatible Three-state Output Driver Functional Block Diagram AT52BC1661A(T) [Preliminary] 24 < ACC < 10 µA @ 3.0V SB0 Clk Gen Row Addresses I/O0 ~ I/O7 I/O8 ~ I/O15 ...
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... Overshoot 1.0V in case of pulse width < Undershoot: -1.0V in case of pulse width < 20 ns. (1) Capacitance ( MHz, T Item Symbol Input Capacitance C I/O Capacitance C Note: 1. Capacitance is sampled, not 100% tested. 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] PLB PUB I/ (1) ( High-Z (1) ( High High-Z ...
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... Current I CC2 Output Low Voltage V OL Output High Voltage V OH Standby Current (TTL Standby Current (CMOS) I SB1 Low Power Modes I SB0 AT52BC1661A(T) [Preliminary] 26 Test Conditions V = PGND PCS1 = POE = V or PWE = PGND to PV I/O CC Cycle time = 1 µs, 100% duty, I ...
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... Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z PCS1 High Pulse Width 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] = 2.7V – 3.3V -25°C to 85° Symbol Speed Bins 70 ns ...
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... Power Up 1. Apply Power. Sequence 2. Maintain stable power for a minimum of 200 µs with PCS1 = V Standby Mode State Machines Standby Mode Standby Mode Characteristics Low Power Modes AT52BC1661A(T) [Preliminary] 28 Power On PCS1 = V Initial State Wait 200 µs PCS1 = V PUB or/and PLB = V Active Mode ...
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... HZ OHZ voltage levels any given temperature and voltage condition, t device interconnection not access device with cycle timing shorter than t 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary PWE = V , PUB or/and PLB = ...
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... PCS1 going low to end of write measured from the address valid to the beginning of write measured from the end of write to the address change not access device with cycle timing shorter than t AT52BC1661A(T) [Preliminary ( (1) P ...
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... Deep Power-down Mode Entry/Exit A4 PCS1 PUB, PLB PWE ZWE ZZ Parameter t ZZWE t (Deep Power-down Mode Only ZZmin 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] C (4) R ( ZZmin Register Deep Power Write (DPD) Down Start Description ZZ low to Write Enable Low Operation Recovery Time ...
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... Ordering Information t (ns) Voltage Range Ordering Code ACC 70 2.7V - 3.3V AT52BC1661AT-70CI 70 2.7V - 3.3V AT52BC1661A-70CI 66C5 66-ball, Plastic Chip-scale Ball Grid Array Package (CBGA) AT52BC1661A(T) [Preliminary] 32 Flash Boot PSRAM Block Size Top 8-Mbit 8-Mbit Bottom Package Type Package Operation Range Extended 66C5 (-25° to 85°C) Extended 66C5 (-25° ...
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... D 0.60 REF Øb 2325 Orchard Parkway San Jose, CA 95131 R 3455A–STKD–11/04 AT52BC1661A(T) [Preliminary] E Top View E1 A1 Ball Corner e 1.20 REF Bottom View TITLE 66C5, 66-ball ( Array 1.2 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) 0 ...
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... Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2004. All rights reserved. Atmel are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...