am41pds3228d Meet Spansion Inc., am41pds3228d Datasheet - Page 12

• Manufacturer Part Number: am41pds3228d
• Description: 32 Mbit 2 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation Page Mode Flash Memory And 8 Mbit 1 M ? 8-bit/512 K ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

Legend: L = Logic Low = V
SADD = Flash Sector Address, A
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = V
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
6. If WP#/ACC = V
May 13, 2002
Operation
(Notes 1, 2)
Read from Flash
Write to Flash
Standby
Output Disable
Flash Hardware
Reset
Sector Protect (Note
5)
Sector Unprotect
(Note 5)
Temporary Sector
Unprotect
Read from SRAM
Write to SRAM
If WP#/ACC = V
and Unprotection” section.
whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC =
V
HH,
all sectors will be unprotected.
IL
ACC
IL
, the two outermost boot sectors remain protected. If WP#/ACC = V
, the boot sectors will be protected. If WP#/ACC = V
(9V), the program time will be reduced by 40%.
V
CE#f
0.3 V
CC
H
H
IL
X
X
L
L
L
L
L
, CE1#s = V
IL
Table 2. Device Bus Operations—SRAM Byte Mode, CIOs = V
, H = Logic High = V
CE1#s CE2s OE# WE#
IN
H
X
H
X
H
X
H
X
H
X
H
X
H
X
L
L
L
= Address In, D
IL
and CE2s = V
X
X
X
H
X
X
X
X
H
H
L
L
L
L
L
L
L
IH
H
H
H
H
L
X
X
X
L
X
, V
IN
ID
= Data In, D
P R E L I M I N A R Y
IH
= 9–11 V, V
at the same time.
H
H
H
X
X
X
L
L
L
L
Am41PDS3228D
SA
SA
SA
SA
X
X
X
X
X
X
X
OUT
HH
A1 = H,
A6 = H,
A1 = H,
= Data Out, DNU = Do Not Use
A6 = L,
SADD,
SADD,
A0 = L
A0 = L
= 9.0 ± 0.5 V, X = V
Addr.
IH
A
A
A
A
A
X
X
X
the boot sectors protection will be removed.
IN
IN
IN
IN
IN
(Note 3)
LB#s
DNU
X
X
X
X
X
X
X
X
X
IH
, the two outermost boot sector protection depends on
IL
(Note 3)
UB#s
or V
DNU
X
X
X
X
X
X
X
X
X
IH
, SA = SRAM Address Input, Byte Mode,
RESET#
V
0.3 V
V
V
V
CC
H
H
H
H
H
L
ID
ID
ID
SS
WP#/ACC
(Note 4)
(Note 3)
(Note 6)
(Note 6)
L/H
L/H
L/H
L/H
H
X
X
High-Z
High-Z
High-Z
DQ7–
D
D
DQ0
D
D
D
D
D
OUT
OUT
IN
IN
IN
IN
IN
DQ15–
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
DQ8
D
OUT
X
X
IN
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