s71pl512nd0 Meet Spansion Inc., s71pl512nd0 Datasheet - Page 71

• Manufacturer Part Number: s71pl512nd0
• Description: Two S29pl256n Devices 32 M X 16-bit Cmos 3.0-volt Only Simultaneous Read/write, Page-mode Flash Memory
• Manufacturer: Meet Spansion Inc.

November 23, 2005 S29PL-N_M0_A4
Term
Page Read
Password Protection
Persistent Protection
Program
Program Suspend/Program
Resume
Read
Registers
Secured Silicon
Sector Protection
Sector
Simultaneous Operation
Synchronous Operation
VersatileIO™ (V
Unlock Bypass
Word
IO
)
Definition
Asynchronous read operation of several words in which the first word of the group
takes a longer initial access time and subsequent words in the group take less page
access time to be read. Different words in the group are accessed by changing only the
least significant address lines.
Sector protection method which uses a programmable password, in addition to the
Persistent Protection method, for protection of sectors in the Flash memory device.
Sector protection method that uses commands and only the standard core voltage
supply to control protection of sectors in the Flash memory device. This method
replaces a prior technique of requiring a 12V supply to control the protection method.
Stores data into a Flash memory by selectively clearing bits of the memory array to
leave a data pattern of ones and zeros.
Halts a programming operation to read data from any location that is not selected for
programming or erase.
Host bus cycle that causes the Flash to output data onto the data bus.
Dynamic storage bits for holding device control information or tracking the status of
an operation.
An area consisting of 256 bytes in which any word may be programmed once, and the
entire area may be protected once from any future programming. Information in this
area may be programmed at the factory or by the user. Once programmed and
protected there is no way to change the secured information. This area is often used
to store a software readable identification such as a serial number.
Use of one or more control bits per sector to indicate whether each sector may be
programmed or erased. If the Protection bit for a sector is set the embedded
algorithms for program or erase ignore the program or erase commands related to that
sector.
An Area of the memory array in which all bits must be erased together by an erase
operation.
Mode of operation in which a host system may issue a program or erase command to
one bank, that embedded algorithm operation may then proceed while the host
immediately follows the embedded algorithm command with reading from another
bank. Reading may continue concurrently in any bank other than the one executing
the embedded algorithm operation.
Operation that progresses only when a timing signal, known as a clock, transitions
between logic levels (that is, at a clock edge).
Separate power supply or voltage reference signal that allows the host system to set
the voltage levels that the device generates at its data outputs and the voltages
tolerated at its data inputs.
Mode that facilitates faster program times by reducing the number of command bus
cycles required to issue a write operation command. In this mode the initial two Unlock
write cycles, of the usual 4 cycle Program command, are not required – reducing all
Program commands to two bus cycles while in this mode.
Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two
contiguous words located on a two word boundary. A quad word is four contiguous
words located on a four word boundary.
P r e l i m i n a r y
S29PL-N MirrorBit™ Flash Family
69