s71pl512nd0 Meet Spansion Inc., s71pl512nd0 Datasheet - Page 13

• Manufacturer Part Number: s71pl512nd0
• Description: Two S29pl256n Devices 32 M X 16-bit Cmos 3.0-volt Only Simultaneous Read/write, Page-mode Flash Memory
• Manufacturer: Meet Spansion Inc.

General Description
Distinctive Characteristics
Architectural Advantages
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Performance Characteristics
product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and
quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that
S29PL-N MirrorBit™ Flash Family
S29PL256N, S29PL127N, S29PL129N, 
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only
Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
Random Access Time, ns (t
Page Access Time, ns (t
Max CE# Access Time, ns (t
Max OE# Access Time, ns (t
8-Word Page Read
Simultaneous Read/Write
Program/Erase
Standby
The Spansion S29PL-N is the latest generation 3.0-Volt page mode read family fabricated using the 110 nm Mirrorbit
Flash process technology. These 8-word page-mode Flash devices are capable of performing simultaneous read and write
operations with zero latency on two separate banks. These devices offer fast page access times of 25 to 30 ns, with
corresponding random access times of 65 ns, 70 ns, and 80 ns respectively, allowing high speed microprocessors to op-
erate without wait states. The S29PL129N device offers the additional feature of dual chip enable inputs (CE1# and
CE2#) that allow each half of the memory space to be controlled separately.
32-Word Write Buffer
Dual Chip Enable Inputs (only for S29PL129N)
— Two CE# inputs control selection of each half of the
Single Power Supply Operation
— Full Voltage range of 2.7 – 3.6 V read, erase, and
— Voltage range of 2.7 – 3.1 V valid for PL-N MCP
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
— Zero latency switching from write to read operations
4-Bank Sector Architecture with Top and Bott om
Boot Blocks
256-Word Secured Silicon Sector Region
— Up to 128 factory-locked words
— Up to 128 customer-lockable words
Manufactured on 0.11 µm Process Technology
Data Retention of 20 years Typical
Cycling Endurance of 100,000 Cycles per Sector
Typical
memory space
program operations for battery-powered applications
products
executing erase/program functions in another bank
Read Access Times (@ 30 pF, Industrial Temp.)
Current Consumption (typical values)
Publication Number S29PL-N_M0 Revision A Amendment 4 Issue Date November 23, 2005
PACC
ACC
)
CE
OE
)
)
)
65
25
65
25
70
30
70
30
65 mA
25 mA
20 µA
6 mA
80
30
80
30
Hardware Features
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Security Features
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Note:
conditions: 25°C, 3.0 V V
Typical Word
Typical Effective Word (32 words in buffer)
Accelerated Write Buffer Program
Typical Sector Erase Time (32-Kword Sector)
Typical Sector Erase Time (128-Kword Sector)
S29PL-N
256
129
127
WP#/ACC (Write Protect/Acceleration) Input
— At V
— At V
— At V
Dual Boot and No Boot Options
Low V
Persistent Sector Protection
— A command sector protection method to lock
— Sectors can be locked and unlocked in-system at V
Password Sector Protection
— A sophisticated sector protection method locks
: Typical program and erase times assume the following
two 32 Kword sectors.
factory setting
combinations of individual sectors to prevent
program or erase operations within that sector
level
combinations of individual sectors to prevent program
or erase operations within that sector using a user
defined 64-bit password
Typical Program & Erase Times (typical values) (See Note)
CC
IL
8.0 x 11.6 mm,
IH
HH
, hardware level protection for the first and last
, allows the use of DYB/PPB sector protection
Write Inhibit
, provides accelerated programming in a
VBH064
64-ball
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CC
, 10,000 cycles; checkerboard data pattern.
Package Options
8.0 x 11.6 mm,
VBH084
84-ball
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PRELIMINARY
11 x 13 mm, 64-ball
Fortified BGA
LAA064
300 ms
9.4 µs
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40 µs
1.6 s
6 µs
TM
CC